K9W4G08U1MK9K2G08Q0MK9K2G08U0MK9W4G16U1MK9K2G16Q0MK9K2G16U0M
FLASH MEMORY
Document Title256M x 8 Bit / 128M x 16 Bit NAND Flash MemoryRevision HistoryRevision No0.00.1
History1. Initial issue
1. IOL(R/B) of 1.8V device is changed.-min. Value: 7mA -->3mA-typ. Value: 8mA -->4mA
Draft DateAug. 30.2001Nov. 5.2001
RemarkAdvance
0.2
1. 5th cycle of ID is changed : 40h --> 44h
1. Add WSOP Package Dimensions.
1. Add two-K9K2GXXU0M-YCB0/YIB0 Stacked Package1. Min valid block of K9W4GXXU1M-YCB0/YIB0 is changed .- min. 4016 --> 4036
1. Each K9K2GXXX0M chip in the K9W4GXXU1M has Maximum 30
Jan. 23. 2002
0.30.40.5
May.29.2002Aug.13.2002Aug. 22.2002
0.6Nov. 07.2002
invalid blocks.
2. K9W4GXXU1M’s ID is changed(Before)
DeviceK9W4G08U1MK9W4G16U1M(After)
DeviceK9W4G08U1MK9W4G16U1M
2nd Cycle3rd cycleDAhCAh
C1C1
4th Cycle15h55h
5th Cycle44h44h
2nd Cycle3rd cycle4th Cycle5th CycleDChCCh
C3C3
15h55h
4Ch4Ch
0.7
1. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 36)
2. Add the data protection Vcc guidence for 1.8V device - below about 1.1V. Nov. 22.2002(Page 37)
The min. Vcc value 1.8V devices is changed.
K9K2GXXQ0M : Vcc 1.65V~1.95V --> 1.70V~1.95V
Mar. 6.2003
0.8
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you haveany questions, please contact the SAMSUNG branch office near your office.
1
元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MK9W4G16U1MK9K2G16Q0MK9K2G16U0M
FLASH MEMORY
Document Title256M x 8 Bit / 128M x 16 Bit NAND Flash Memory
Revision HistoryRevision No0.9
History
Pb-free Package is added.K9K2G08U0M-FCB0,FIB0K9K2G08Q0M-PCB0,PIB0K9K2G08U0M-PCB0,PIB0K9K2G16U0M-PCB0,PIB0K9K2G16Q0M-PCB0,PIB0
K9W4G08U1M-PCB0,PIB0,ECB0,EIB0K9W4G16U1M-PCB0,PIB0,ECB0,EIB0
Errata is added.(Front Page)-K9K2GXXQ0M
tWC tWP tWH tRC tREH tRP tREA tCEASpecification 45 25 15 50 15 25 30 45Relaxed value 80 60 20 80 20 60 60 751. The 3rd Byte ID after 90h ID read command is don’t cared. The 5th Byte ID after 90h ID read command is deleted.New package dimension is added.(K9W4GXXU1M-KXB0/EXB0)1. Min valid block of K9W4GXXU1M-YCB0/YIB0 is changed .
- min. 4036 --> 40162. Note is added.
(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.)
AC parameters are changed-K9K2GXXQ0M
tWC tWP tWH tRC tREH tRP tREA tCEABefore 45 25 15 50 15 25 30 45After 80 60 20 80 20 60 60 75
Draft Date
Mar. 13.2003
Remark
1.0Mar. 17.2003
1.1Apr. 9. 2003
1.21.3
Apr. 15. 2003Apr. 18. 2003
Aug. 5. 2003
1.4
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you haveany questions, please contact the SAMSUNG branch office near your office.
2
元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MK9W4G16U1MK9K2G16Q0MK9K2G16U0M
FLASH MEMORY
256M x 8 Bit / 128M x 16 Bit NAND Flash Memory
PRODUCT LIST
Part NumberK9K2G08Q0M-Y,PK9K2G16Q0M-Y,PK9XXG08UXM-Y,P,K,EK9XXG16UXM-Y,P,K,EK9K2G08U0M-V,F
2.7 ~ 3.6VVcc Range1.7 ~ 1.95V
Organization
X8X16X8X16X8
WSOP1TSOP1PKG Type
FEATURES
• Voltage Supply
-1.8V device(K9K2GXXQ0M): 1.7V~1.95V -3.3V device(K9XXGXXUXM): 2.7 V ~3.6 V• Organization
- Memory Cell Array
-X8 device(K9K2G08X0M) : (256M + 8,192K)bit x 8bit -X16 device(K9K2G16X0M) : (128M + 4,096K)bit x 16bit - Data Register
-X8 device(K9K2G08X0M): (2K + 64)bit x8bit -X16 device(K9K2G16X0M): (1K + 32)bit x16bit - Cache Register
-X8 device(K9K2G08X0M): (2K + 64)bit x8bit -X16 device(K9K2G16X0M): (1K + 32)bit x16bit • Automatic Program and Erase - Page Program
-X8 device(K9K2G08X0M): (2K + 64)Byte -X16 device(K9K2G16X0M): (1K + 32)Word - Block Erase
-X8 device(K9K2G08X0M): (128K + 4K)Byte -X16 device(K9K2G16X0M): (64K + 2K)Word• Page Read Operation - Page Size
- X8 device(K9K2G08X0M): 2K-Byte - X16 device(K9K2G16X0M) : 1K-Word - Random Read : 25µs(Max.) - Serial Access
1.8V device(K9K2GXXQ0M): 80ns(Min.) 3.3V device(K9XXGXXUXM): 50ns(Min.)
• Fast Write Cycle Time
- Program time : 300µs(Typ.) - Block Erase Time : 2ms(Typ.)
• Command/Address/Data Multiplexed I/O Port• Hardware Data Protection
- Program/Erase Lockout During Power Transitions• Reliable CMOS Floating-Gate Technology - Endurance : 100K Program/Erase Cycles - Data Retention : 10 Years• Command Register Operation
• Cache Program Operation for High Performance Program• Power-On Auto-Read Operation• Intelligent Copy-Back Operation• Unique ID for Copyright Protection• Package :
- K9K2GXXX0M-YCB0/YIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9K2G08U0M-VCB0/VIB0
48 - Pin WSOP I (12X17X0.7mm) - K9K2GXXX0M-PCB0/PIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package - K9K2G08U0M-FCB0/FIB0
48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package * K9K2G08U0M-V,F(WSOPI ) is the same device as K9K2G08U0M-Y,P(TSOP1) except package type.
- K9W4GXXU1M-YCB0,PCB0/YIB0,PIB0 : Two K9K2G08U0M stacked.
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9W4GXXU1M-KCB0,ECB0/KIB0,EIB0 : Two K9K2G08U0M stacked.
48 - Pin TSOP I (12 x 17 / 0.5 mm pitch)
GENERAL DESCRIPTION
Offered in 256Mx8bit or 128Mx16bit, the K9K2GXXX0M is 2G bit with spare 64M bit capacity. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation can be performed in typical 300µs on the 2112-byte(X8device) or 1056-word(X16 device) page and an erase operation can be performed in typical 2ms on a 128K-byte(X8 device) or 64K-word(X16 device) block. Data in the data page can be read out at 80ns(1.8V device) or 50ns(3.3V device) cycle time per byte(X8device) or word(X16 device). The I/O pins serve as the ports for address and data input/output as well as command input. The on-chipwrite controller automates all program and erase functions including pulse repetition, where required, and internal verification andmargining of data. Even the write-intensive systems can take advantage of the K9K2GXXX0M′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9K2GXXX0M is an optimum solu-tion for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.An ultra high density solution having two 2Gb stacked with two chip selects is also available in standard TSOPI package.
3
元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MK9W4G16U1MK9K2G16Q0MK9K2G16U0M
FLASH MEMORY
PIN CONFIGURATION (TSOP1)
K9K2GXXX0M-YCB0,PCB0/YIB0,PIB0
X16
N.CN.CN.CN.CN.CN.CR/B RECEN.CN.CVccVssN.CN.CCLEALEWEWPN.CN.CN.CN.CN.C
X8
N.CN.CN.CN.CN.CN.CR/B RECEN.CN.CVccVssN.CN.CCLEALEWEWPN.CN.CN.CN.CN.C
123456789101112131415161718192021222324
484746454443424140393837363534333231302928272625
X8
N.CN.CN.CN.CI/O7I/O6I/O5I/O4N.CN.CPREVccVssN.CN.CN.CI/O3I/O2I/O1I/O0N.CN.CN.CN.C
X16
VssI/O15I/O7I/O14I/O6I/O13I/O5I/O12I/O4N.CPREVccN.CN.CN.CI/O11I/O3I/O10I/O2I/O9I/O1I/O8I/O0Vss
48-pin TSOP1Standard Type12mm x 20mm
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)48 - TSOP1 - 1220F
Unit :mm/Inch
0.10 MAX0.004 #48
(0.25)0.01012.400.488MAX0.500.0197#24
#25
1.00±0.050.039±0.002
0.250.010TYP18.40±0.100.724±0.004
+0.07520.00±0.200.787±0.008
0.008-0.001+0.0030.20-0.03+0.07#1
12.000.4720.05
0.002MIN
0.1250.0350~8°
0.45~0.750.018~0.030(0.50)0.0204
0.005-0.001+0.0031.20
0.047MAX元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MK9W4G16U1MK9K2G16Q0MK9K2G16U0M
FLASH MEMORY
PIN CONFIGURATION (WSOP1)
K9K2G08U0M-VCB0,FCB0/VIB0,FIB0N.CN.CDNUN.CN.CN.CR/B RECEDNUN.CVccVssN.CDNUCLEALEWEWPN.CN.CDNUN.CN.C
123456789101112131415161718192021222324
484746454443424140393837363534333231302928272625
N.CN.CDNUN.CI/O7I/O6I/O5I/O4N.CDNUN.CVccVssN.CDNUN.CI/O3I/O2I/O1I/O0N.CDNUN.CN.C
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)48 - WSOP1 - 1217F
Unit :mm
0.70 MAX
15.40±0.10
0.58±0.04
#1
+0.07-0.03#48
+0.07-0.030.1612.00±0.100.50TYP(0.50±0.06)0.20#24#25
(0.1Min)
0.0750.10+-0.0350°~8°0.45~0.75
17.00±0.20
5
元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MK9W4G16U1MK9K2G16Q0MK9K2G16U0M
FLASH MEMORY
PIN CONFIGURATION (TSOP1)
K9W4G08U1M-YCB0,PCB0/YIB0,PIB0
X16
N.CN.CN.CN.CN.CR/B2R/B1 RECE1CE2N.CVccVssN.CN.CCLEALEWEWPN.CN.CN.CN.CN.C
X8
N.CN.CN.CN.CN.CR/B2R/B1 RECE1CE2N.CVccVssN.CN.CCLEALEWEWPN.CN.CN.CN.CN.C
123456789101112131415161718192021222324
484746454443424140393837363534333231302928272625
X8
N.CN.CN.CN.CI/O7I/O6I/O5I/O4N.CN.CPREVccVssN.CN.CN.CI/O3I/O2I/O1I/O0N.CN.CN.CN.C
X16
VssI/O15I/O7I/O14I/O6I/O13I/O5I/O12I/O4N.CPREVccN.CN.CN.CI/O11I/O3I/O10I/O2I/O9I/O1I/O8I/O0Vss
48-pin TSOP1Standard Type12mm x 20mm
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)48 - TSOP1 - 1220F
Unit :mm/Inch
0.10 MAX0.004 #48
(0.25)0.01012.400.488MAX0.500.0197#24
#25
1.05±0.030.039±0.002
0.250.010TYP18.40±0.100.724±0.004
1.20
0.047MAX0.02
0.002MIN
+0.07520.00±0.200.787±0.008
0.008-0.001+0.0030.16-0.03+0.07#1
0~8°
0.45~0.750.018~0.030(0.50)0.0206
0.005-0.0010.1250.035+0.00312.000.472元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MK9W4G16U1MK9K2G16Q0MK9K2G16U0M
FLASH MEMORY
PIN CONFIGURATION (TSOP1)
X16
N.CN.CN.CN.CN.CR/B2R/B1 RECE1CE2N.CVccVssN.CN.CCLEALEWEWPN.CN.CN.CN.CN.C
X8
N.CN.CN.CN.CN.CR/B2R/B1 RECE1CE2N.CVccVssN.CN.CCLEALEWEWPN.CN.CN.CN.CN.C
123456789101112131415161718192021222324
K9W4G08U1M-KCB0,ECB0/KIB0,EIB0
484746454443424140393837363534333231302928272625
X8
N.CN.CN.CN.CI/O7I/O6I/O5I/O4N.CN.CPREVccVssN.CN.CN.CI/O3I/O2I/O1I/O0N.CN.CN.CN.C
X16
VssI/O15I/O7I/O14I/O6I/O13I/O5I/O12I/O4N.CPREVccN.CN.CN.CI/O11I/O3I/O10I/O2I/O9I/O1I/O8I/O0Vss
48-pin TSOP112mm x 17mm
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE (I)48 - TSOP1 - 1217F
Unit :mm
1.15 MAX
15.40±0.10
1.00±0.03
#1
+0.07-0.03#48
+0.07-0.030.1612.00±0.100.50TYP(0.50±0.06)0.20#24#25
(0.02Min)
0.0750.15+-0.0350°~8°0.45~0.75
17.00±0.20
7
元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0M
PIN DESCRIPTION
Pin NameI/O0 ~ I/O7(K9K2G08X0M)I/O0 ~ I/O15(K9K2G16X0M)
K9W4G16U1MK9K2G16Q0MK9K2G16U0M
FLASH MEMORY
Pin Function
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled.
I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper-ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and output.
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high.
CHIP ENABLE
The CE / CE1 input is the device selection control. When the device is in the Busy state, CE / CE1 high is ignored, and the device does not return to standby mode in program or erase opertion. Regarding CE / CE1 control during read operation, refer to ’Page read’ section of Device operation .CHIP ENABLE
The CE2 input enables the second K9K2GXXU0M
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low.
READY/BUSY OUTPUT
The R/B / R/B1 output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.READY/BUSY OUTPUT
The R/B2 output indicates the status of the second K9K2GXXU0M
POWER-ON READ ENABLE
The PRE controls auto read operation executed during power-on. The power-on auto-read is enabled when PRE pin is tied to Vcc.
POWER
VCC is the power supply for device. GROUND
NO CONNECTION
Lead is not internally connected.
CLE
ALE
CE / CE1
CE2
RE
WE
WP
R/B / R/B1
R/B2
PRE
VccVssN.C
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected.
8
元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MK9W4G16U1MK9K2G16Q0MK9K2G16U0MFLASH MEMORYFigure 1-1. K9K2G08X0M (X8) Functional Block DiagramVCCVSSA12 - A28X-BuffersLatches& DecodersY-BuffersLatches& Decoders2048M + 64M BitNAND FlashARRAY(2048 + 64)Byte x 131072 Data Register & S/ACache RegisterCommandCommandRegisterY-GatingA0 - A11I/O Buffers & LatchesVCCVSSOutputDriverI/0 0CEREWEControl Logic& High VoltageGeneratorGlobal BuffersI/0 7CLEALE PREWPFigure 2-1. K9K2G08X0M (X8) Array Organization1 Block = 64 Pages(128K + 4k) Byte 128K Pages(=2,048 Blocks)8 bit 2K Bytes64 Bytes1 Page = (2K + 64)Bytes1 Block = (2K + 64)B x 64 Pages = (128K + 4K) Bytes1 Device = (2K+64)B x 64Pages x 2048 Blocks = 2112 MbitsPage Register 2K BytesI/O 01st Cycle2nd Cycle3rd Cycle4th Cycle5th CycleA0A8A12A20A28I/O 1A1A9A13A21*LI/O 2A2A10A14A22*L64 BytesI/O 3A3A11A15A23*LI/O 0 ~ I/O 7I/O 4A4*LA16A24*LI/O 5A5*LA17A25*LI/O 6A6*LA18A26*LI/O 7A7*LA19A27*LColumn AddressColumn AddressRow AddressRow AddressRow AddressNOTE : Column Address : Starting Address of the Register.* L must be set to \"Low\".* The device ignores any additional input of address cycles than reguired.9元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MK9W4G16U1MK9K2G16Q0MK9K2G16U0MFLASH MEMORYFigure 1-2. K9K2G16X0M (X16) Functional Block DiagramVCCVSSA11 - A27X-BuffersLatches& DecodersY-BuffersLatches& Decoders2048M + 64M BitNAND FlashARRAY(1024 + 32)Word x 131072 Data Register & S/ACache RegisterCommandCommandRegisterY-GatingA0 - A10I/O Buffers & LatchesVCCVSSOutputDriverI/0 0CEREWEControl Logic& High VoltageGeneratorGlobal BuffersI/0 15CLEALE PREWPFigure 2-2. K9K2G16X0M (X16) Array Organization1 Block = 64 Pages(64K + 2k) Word128K Pages(=2,048 Blocks)16 bit 1K Words32 Words1 Page = (1K + 32)Words1 Block = (1K + 32)Word x 64 Pages = (64K + 2K) Words1 Device = (1K+32)Word x 64Pages x 2048 Blocks = 2112 MbitsPage Register 1K WordsI/O 01st Cycle2nd Cycle3rd Cycle4th Cycle5th CycleA0A8A11A19A27I/O 1A1A9A12A20*LI/O 2A2A10A13A21*LI/O 3A3*LA14A22*L32 WordsI/O 4A4*LA15A23*LI/O 0 ~ I/O 15I/O 5A5*LA16A24*LI/O 6A6*LA17A25*LI/O 7A7*LA18A26*LI/O8 ~ 15*L*L*L*L*LColumn AddressColumn AddressRow AddressRow AddressRow AddressNOTE : Column Address : Starting Address of the Register.* L must be set to \"Low\".* The device ignores any additional input of address cycles than reguired.10元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MK9W4G16U1MK9K2G16Q0MK9K2G16U0M
FLASH MEMORY
Product Introduction
The K9K2GXXX0M is a 2112Mbit(2,214,592,512 bit) memory organized as 131,072 rows(pages) by 2112x8(X8 device) or1056x16(X16 device) columns. Spare 64(X8) or 32(X16) columns are located from column address of 2048~2111(X8 device) or1024~1055(X16 device). A 2112-byte(X8 device) or 1056-word(X16 device) data register and a 2112-byte(X8 device) or 1056-word(X16 device) cache register are serially connected to each other. Those serially connected registers are connected to memorycell arrays for accommodating data transfer between the I/O buffers and memory cells during page read and page program opera-tions. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in adifferent page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total 1081344 NAND cellsreside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a blockbasis. The memory array consists of 2048 separately erasable 128K-byte(X8 device) or 64K-word(X16 device) blocks. It indicatesthat the bit by bit erase operation is prohibited on the K9K2GXXX0M.
The K9K2GXXX0M has addresses multiplexed into 8 I/Os(X16 device case : lower 8 I/Os). This scheme dramatically reduces pincounts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address anddata are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command LatchEnable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some com-mands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some othercommands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execu-tion. The 256M byte(X8 device) or 128M word(X16 device) physical space requires 29(X8) or 28(X16) addresses, thereby requiringfour cycles for addressing: 2 cycles of column address, 3 cycles of row address, in that order. Page Read and Page Program needthe same four address cycles following the required command input. In Block Erase operation, however, only the two row addresscycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specificcommands of the K9K2GXXX0M.
The device provides cache program in a block. It is possible to write data into the cache registers while data stored in data registersare being programmed into memory cells in cache program mode. The program performace may be dramatically improved by cacheprogram when there are lots of pages of data to be programmed.
The device embodies power-on auto-read feature which enables serial access of data of the 1st page without command and addressinput after power-on.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to anotherpage without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access anddata-input cycles are removed, system performance for solid-state disk application is significantly increased.
Table 1. Command Sets
Function
Read for Copy BackRead IDResetPage ProgramCache ProgramCopy-Back ProgramBlock EraseRandom Data Input*Random Data Output*Read Status
1st. Cycle
00h90hFFh80h80h85h60h85h05h70h
2nd. Cycle
30h35h--10h15h10hD0h-E0h
OO
Acceptable Command during Busy
Read 00hNOTE : 1. Random Data Input/Output can be executed in a page.
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
11
元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MK9W4G16U1MK9K2G16Q0MK9K2G16U0M
FLASH MEMORY
Rating
K9K2GXXQ0M(1.8V) K9XXGXXUXM(3.3V)
-0.6 to + 2.45-0.2 to + 2.45
-10 to +125-40 to +125-65 to +150
5
-0.6 to + 4.6-0.6 to + 4.6
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to VSSTemperature Under BiasStorage TemperatureShort Circuit Current
K9XXGXXXXM-XCB0K9XXGXXXXM-XIB0K9XXGXXXXM-XCB0K9XXGXXXXM-XIB0
SymbolVIN/OUTVCCTBIASTSTGIos
UnitV°C°CmA
NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9XXGXXXXM-XCB0 :TA=0 to 70°C, K9XXGXXXXM-XIB0:TA=-40 to 85°C)
ParameterSupply VoltageSupply Voltage
SymbolVCCVSS
K9K2GXXQ0M(1.8V)Min1.70
Typ.1.80
Max1.950
Min2.70
K9XXGXXUXM(3.3V)
Typ.3.30
Max3.60
UnitVV
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Parameter
Operat-Page Read with
Serial Access
ing
CurrentProgram
Erase
Stand-by Current(TTL)Stand-by Current(CMOS)Input Leakage CurrentOutput Leakage CurrentInput High Voltage
Input Low Voltage, All inputsOutput High Voltage LevelOutput Low Voltage Level
SymbolICC1ICC2ICC3ISB1ISB2ILIILOVIH*VIL*VOHVOLIOL(R/B)
CE=VCC-0.2, WP=PRE=0V/VCCVIN=0 to Vcc(max)VOUT=0 to Vcc(max)
--K9K2GXXQ0M:IOH=-100µAK9XXGXXUXM:IOH=-400µAK9K2GXXQ0M :IOL=100uAK9XXGXXUXM :IOL=2.1mAK9K2GXXQ0M :VOL=0.1VK9XXGXXUXM :VOL=0.4V
Test ConditionstRC=50ns, CE=VILIOUT=0mA
--CE=VIH, WP=PRE=0V/VCC
K9K2GXXQ0M(1.8V)Min-------VCC-0.4-0.3Vcc-0.1
-3
Typ101010-20------4
Max2020201100±20±20VCC+0.30.4-0.1-K9XXGXXUXM(3.3V)Min-------2.0-0.32.4-8
Typ151515-20------10
Max3030301100±20±20VCC+0.30.8-0.4-mAVµAmAUnit
Output Low Current(R/B)
NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.
12
元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0M
VALID BLOCK
K9W4G16U1MK9K2G16Q0MK9K2G16U0M
FLASH MEMORY
SymbolNVBNVB
Min20084016*
Max20484096*
UnitBlocksBlocks
Parameter
K9K2GXXX0MK9W4GXXU1M
Valid Block NumberValid Block Number
NOTE :
1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-gram factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erasecycles.
* : Each K9K2GXXX0M chip in the K9W4GXXU1M has Maximum 40 invalid blocks.
AC TEST CONDITION
(K9XXGXXXXM-XCB0 :TA=0 to 70°C, K9XXGXXXXM-XIB0:TA=-40 to 85°C
K9K2GXXQ0M : Vcc=1.70V~1.95V , K9XXGXXUXM : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
Input Pulse LevelsInput Rise and Fall TimesInput and Output Timing Levels
K9K2GXXQ0M:Output Load (Vcc:1.8V +/-10%)K9XXGXXUXM:Output Load (Vcc:3.0V +/-10%)K9XXGXXUXM:Output Load (Vcc:3.3V +/-10%)
K9K2GXXQ0M0V to Vcc5nsVcc/2
1 TTL GATE and CL=30pF
-K9XXGXXUXM0.4V to 2.4V
5ns1.5V
1 TTL GATE and CL=50pF1 TTL GATE and CL=100pF
CAPACITANCE(TA=25°C, VCC=1.8V/3.3V, f=1.0MHz)
Item
Input/Output CapacitanceInput Capacitance
SymbolCI/OCIN
Test Condition
VIL=0VVIN=0V
Max
K9K2GXXX0M
2020
K9W4GXXU1M
4040
UnitpFpF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLEHLHLLLXXXXX
ALELHLHLLXXXX(1)X
CELLLLLLXXXXH
HXXXXX
HXXXX
WE
REHHHHH
WPXXHHHX XHHL0V/VCC(2)
PREXXXXXX XXXX
Data Input Data Output During Read(Busy) During Program(Busy) During Erase(Busy) Write ProtectRead ModeWrite Mode
Mode Command Input Address Input(5clock) Command Input Address Input(5clock)
0V/VCC(2) Stand-by
NOTE : 1. X can be VIL or VIH.
2. WP and PRE should be biased to CMOS high or CMOS low for standby.
13
元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MK9W4G16U1MK9K2G16Q0MK9K2G16U0M
FLASH MEMORY
Sym-tPROGtCBSY
Min----Typ3003--2
Max700700443
Unitµsµscyclescyclesms
Program / Erase Characteristics
Parameter
Program Time Dummy Busy Time for Cache Program Number of Partial Program Cyclesin the Same PageBlock Erase Time
Main ArraySpare Array
NoptBERS
NOTE : 1. Max. time of tCBSY depends on timing between internal program completion and data in
AC Timing Characteristics for Command / Address / Data Input
ParameterCLE setup TimeCLE Hold TimeCE setup TimeCE Hold TimeWE Pulse WidthALE setup TimeALE Hold TimeData setup TimeData Hold TimeWrite Cycle TimeWE High Hold Time
SymboltCLStCLHtCStCHtWPtALStALHtDStDHtWCtWH
Min
K9K2GXXQ0M
0100106001020108020
K9K2GXXU0M
01001025(1)01020104515
-----------Max
K9K2GXXQ0M
K9K2GXXU0M
-----------Unitnsnsnsnsnsnsnsnsnsnsns
NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
AC Characteristics for Operation
Parameter
Data Transfer from Cell to RegisterALE to RE DelayCLE to RE DelayReady to RE LowRE Pulse WidthWE High to BusyRead Cycle TimeRE Access TimeCE Access TimeRE High to Output Hi-ZCE High to Output Hi-ZRE or CE High to Output hold RE High Hold TimeOutput Hi-Z to RE LowWE High to RE LowDevice Resetting Time(Read/Program/Erase)
SymboltRtARtCLRtRRtRPtWBtRCtREAtCEAtRHZtCHZtOHtREHtIRtWHRtRST
MinK9K2GXXQ0M
-10102060-80----1520060-MinK9K2GXXU0M
-10102025-50----1515060-MaxK9K2GXXQ0M
25----100-60753020----5/10/500(1)
MaxK9K2GXXU0M
25----100-30453020----5/10/500(1)
Unitµsnsnsnsnsnsnsnsnsnsnsnsnsnsnsµs
NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
14
元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MK9W4G16U1MK9K2G16Q0MK9K2G16U0M
FLASH MEMORY
NAND Flash Technical Notes
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor-mation regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same qualitylevel as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the perfor-mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system designmust be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaran-teed to be a valid block, does not require Error Correction up to 1K program/erase cycles.
Identifying Invalid Block(s)
All device locations are erased(FFh for X8, FFFFh for X16) except locations where the invalid block(s) information is written prior toshipping. The invalid block(s) status is defined by the 1st byte(X8 device) or 1st word(X16 device) in the spare area. Samsungmakes sure that either the 1st or 2nd page of every invalid block has non-FFh(X8) or non-FFFFh(X16) data at the column address of2048(X8 device) or 1024(X16 device). Since the invalid block information is also erasable in most cases, it is impossible to recoverthe information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the originalinvalid block information and create the invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure ofthe original invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Create (or update)Invalid Block(s) Table
No
*Check \"FFhor FFFFh\" ?
Yes
Check \"FFh( or FFFFh)\" at the column address 2048(X8 device) or 1024(X16 device)of the 1st and 2nd page in the blockNo
Last Block ?
Yes
End
Figure 3. Flow chart to create invalid block table.
15
元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MK9W4G16U1MK9K2G16Q0MK9K2G16U0M
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Error in write or read operation
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actualdata.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-ure after erase or program, block replacement should be done. Because program status fail during a page program does not affectthe data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erasedempty block and reprogramming the current target data and copying the rest of the replaced block.To improve the efficiency of mem-ory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any blockreplacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode Erase Failure
Write
Program Failure Single Bit Failure
Detection and Countermeasure sequence
Status Read after Erase --> Block Replacement Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement
or ECC Correction Verify ECC -> ECC Correction
Read
ECC: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detection
Program Flow Chart If ECC is used, this verification
operation is not needed.
Start
Write 80h
Write 00h
Write Address
Write Address
Write Data
Write 30h
Write 10h
Wait for tR Time
Read Status Register
Verify Data
Fail*Program Error I/O 6 = 1 ?or R/B = 1 ?
Yes
No
I/O 0 = 0 ?
NoPass
Program Completed
*Program Error * : If program operation results in an error, map out the block including the page in error and copy the target data to another block.
Yes
16
元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MK9W4G16U1MK9K2G16Q0MK9K2G16U0MFLASH MEMORYNAND Flash Technical Notes (Continued)Erase Flow Chart StartWrite 60hWrite Block AddressWrite D0hRead Status RegisterRead Flow Chart StartWrite 00hWrite AddressWrite 30hRead DataECC GenerationI/O 6 = 1 ?or R/B = 1 ?YesNoNo*Erase Error Reclaim the Error Verify ECC Yes Page Read CompletedNoI/O 0 = 0 ? Yes Erase Completed* : If erase operation results in an error, map outthe failing block and replace it with another block. Block Replacement1st(n-1)thnth(page)Block B1{{Block A2 an error occurs. Buffer memory of the controller.1st(n-1)thnth(page)* Step1When an error happens in the nth page of the Block ’A’ during erase or program operation. * Step2Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)* Step3Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.* Step4Do not erase or program to Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.∼∼17元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MK9W4G16U1MK9K2G16Q0MK9K2G16U0MFLASH MEMORYSystem Interface Using CE don’t-care. For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal2112byte(X8 device) or 1056word(X16 device) data registers are utilized as separate buffers for this operation and the system designgets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CEduring the data-loading and serial access would provide significant savings in power consumption.Figure 4. Program Operation with CE don’t-care. CLECE don’t-care CE≈WEALEI/Ox80hAddress(4Cycles)Data Input Data Input ≈10htCSCEtCHCEtCEAtREAtWPWEI/O0~7outREFigure 5. Read Operation with CE don’t-care. CLECE don’t-care CEREALER/BtRWEI/OxData Output(serial access)00hAddress(4Cycle)30h18≈元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MNOTEK9W4G16U1MK9K2G16Q0MK9K2G16U0MFLASH MEMORYADDRESSCol. Add1A0~A7A0~A7Col. Add2A8~A11A8~A10Row Add1A12~A19A11~A18Row Add2A20~A27A19~A26Row Add3A28A27DeviceK9K2G08X0M(X8)K9K2G16X0M(X16) I/OI/OxI/O 0 ~ I/O 7I/O 0 ~ I/O 15DATAData In/Out~2112byte~1056wordCommand Latch CycleCLEtCLStCSCEtCLHtCHtWPWEtALSALEtDSI/OxK9XXG16XXM : I/O8~15 must be set to \"0\"tALHtDHCommandAddress Latch CycletCLSCLEtCSCEtWCtWCtWCtWCtWPWEtALSALEtDSI/OxtDHtWHtALHtALStWPtWHtALHtALStWPtWHtALHtALStWPtWHtALHtALStALHtDStDHtDStDHtDStDHtDStDHCol. Add1Col. Add2Row Add1Row Add2Row Add3K9XXG16XXM : I/O8~15 must be set to \"0\"19元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MK9W4G16U1MK9K2G16Q0MK9K2G16U0MFLASH MEMORYInput Data Latch CycletCLH≈CLEtCHCEtALSALEtWCWEtDSI/OxtWHtDHtDStDH≈tWPtWP≈tWPtDHtDS≈DIN 0DIN 1DIN final*NOTES : DIN final means 2112(X8) or 1056(X16)Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)tCEA≈CE≈≈REtRHZ*I/OxtRRR/BtRHZ*tOHDoutDouttRCDoutNOTES : Transition is measured ±200mV from steady state voltage with load.This parameter is sampled and not 100% tested.20≈≈≈tREAtREHtREAtREAtCHZ*tOH元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MStatus Read CycleK9W4G16U1MK9K2G16Q0MK9K2G16U0MFLASH MEMORYtCLRCLEtCLStCSCEtCHtCEAtWHRREtDSI/OxK9XXG16XXM : I/O8~15 must be set to \"0\"70htDHtIR*tREAtRHZ*tOHStatus OutputtCHZ*tOHtCLHtWPWE21元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MRead OperationK9W4G16U1MK9K2G16Q0MK9K2G16U0MFLASH MEMORYtCLRCLECEtWCWEtWBtARALEtRREtRRI/Ox00h Col. Add1Col. Add2Row Add1Row Add2Row Add3tRCtRHZ30h ≈≈tCHZtOHDout N+2≈Dout NDout N+1Dout MColumn AddressRow AddressBusyR/BRead Operation(Intercepted by CE)CLECEWEtWBtARALEtRREtRRI/Ox00hCol. Add1Col. Add2Row Add1Row Add2Row Add330htRCDout NDout N+1Column AddressRow AddressR/BBusy22K9W4G08U1MK9K2G08Q0MK9K2G08U0MRandom Data Output In a Page 元器件交易网www.cecb2b.com
CLEtCLRK9W4G16U1MK9K2G16Q0MK9K2G16U0MCEWEtWBtARtWHR23tRtRCALEtREAREtRRRow Add1Row Add2Row Add3I/OxRow Address00hDout NCol. Add1Col. Add230hDout N+105hCol Add1Col Add2E0hDout MDout M+1Column AddressBusyColumn AddressFLASH MEMORYR/B元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MK9W4G16U1MK9K2G16Q0MK9K2G16U0MFLASH MEMORYPage Program OperationCLECEWEtWBALEtPROGREDinDinNM1 up to m ByteSerial InputI/Ox80h≈≈≈tWCtWCtWCCo.l Add1Col. Add2Row Add1Row Add2Row Add310hProgramCommand70hRead StatusCommandI/O0SerialDataColumn AddressInput CommandRow Address≈R/BX8 device : m = 2112byteX16 device : m = 1056wordI/O0=0 Successful ProgramI/O0=1 Error in Program24K9W4G08U1MK9K2G08Q0MK9K2G08U0M元器件交易网www.cecb2b.com
Page Program Operation with Random Data InputK9W4G16U1MK9K2G16Q0MK9K2G16U0MCLECE≈WE≈tWCtWCtWCtWBtPROGSerial DataColumn AddressInput CommandRow AddressSerial Input≈≈Random DataColumn AddressInput CommandSerial Input≈≈Col. Add2≈25Row Add2Row Add3ALEREI/Ox80h85hCol. Add1Col. Add2Row Add1DinNDinMCol. Add1DinJDinK10hProgramCommand70hRead StatusCommandI/O0FLASH MEMORYR/BK9W4G08U1MK9K2G08Q0MK9K2G08U0M元器件交易网www.cecb2b.com
Copy-Back Program Operation With Random Data Input CLEK9W4G16U1MK9K2G16Q0MK9K2G16U0MCEtWCtWBtWBtRtPROGWEColumn AddressRow AddressColumn AddressRow Address≈≈≈BusyCopy-Back DataInput CommandBusyI/O0=0 Successful ProgramI/O0=1 Error in Program≈2635hALEREI/Ox85h00hCol Add1Col Add2Row Add1Row Add2Row Add3Col Add1Col Add2Row Add1Row Add2Row Add3Data 1Data N10h70hI/O0Read StatusCommandR/BFLASH MEMORYCache Program Operation(available only within a block) K9W4G08U1MK9K2G08Q0MK9K2G08U0MCLECE≈≈元器件交易网www.cecb2b.com
tWCWEtWBtCBSYtWBtPROGK9W4G16U1MK9K2G16Q0MK9K2G16U0MALERE≈≈Serial DataColumn AddressInput CommandSerial InputRow Address≈≈I/Ox80hCol Add1Col Add2Row Add1Row Add2Row Add3DinNDinM15hProgramCommand(Dummy)80hCol Add1Col Add2Row Add1Row Add2Row Add3DinNDin10hMProgram ConfirmCommand(True)70hI/OMax. 63 times repeatable≈Last Page Input & Program B S Y : max. 700ust CEx.) Cache ProgramtCBSYtCBSYtCBSYtPROGR/B80h≈27 Address & Data Input15h80h Address & Data Input15hR/BFLASH MEMORYI/Ox80h Address &15h Data InputCol Add1,2 & Row Add1,2Data80h Address & Data Input10h70h元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MK9W4G16U1MK9K2G16Q0MK9K2G16U0MFLASH MEMORYBLOCK ERASE OPERATIONCLECEtWCWEtWBALEtBERSREI/Ox60hRow Add1Row Add2Row Add3D0h70hI/O 0Row AddressAuto Block EraseSetup CommandErase Command≈R/BBusyI/O0=0 Successful EraseRead StatusI/O0=1 Error in EraseCommand28元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0M
Read ID Operation
K9W4G16U1MK9K2G16Q0MK9K2G16U0M
FLASH MEMORY
CLE
CE
WE
tAR
ALE
RE
tREA
I/Ox
90h
Read ID Command
00hAddress. 1cycle
ECh
DeviceCode*
XXh
4th cyc.*Maker CodeDevice Code
DeviceK9K2G08Q0MK9K2G08U0MK9K2G16Q0MK9K2G16U0MK9W4G08U1MK9W4G16U1M
Device Code*(2nd Cycle)
AAhDAhBAhCAh
4th Cycle*
15h15h55h55h
Same as each K9K2G08U0M in itSame as each K9K2G16U0M in it
ID Defintition Table
90 ID : Access command = 90H
Description
1st Byte2nd Byte3rd Byte4th Byte
Maker CodeDevice CodeDon’t care
Page Size, Block Size, Spare Size, Organization
29
元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0M
4th ID Data
K9W4G16U1MK9K2G16Q0MK9K2G16U0M
FLASH MEMORY
I/O7
I/O6
I/O5 I/O4 I/O3
I/O2
I/O1 I/O0 0 0 0 1 1 0 1 1
0 0 0 1 1 0 1 1
0 1
0 1
0011
0101
Description
Page Size
(w/o redundant area )
1KB 2KB
Reserved Reserved 64KB128KB256KBReserved 8 16 x8 x1650ns30ns
ReservedReserved
Blcok Size
(w/o redundant area ) Redundant Area Size ( byte/512byte)Organization
Serial Access minimum
30
元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MDevice OperationPAGE READK9W4G16U1MK9K2G16Q0MK9K2G16U0MFLASH MEMORYUpon initial device power up, the device defaults to Read mode.This operation is also initiated by writing 00h-30h to the commandregister along with five address cycles. In two consecutive read operations, the second one doesn’t need 00h command, which fiveaddress cycles and 30h command initiates that operation. Once the command is latched, it does not need to be written for the follow-ing page read operation. Two types of operations are available : random read, serial page read .The random read mode is enabled when the page address is changed. The 2112 bytes(X8 device) or 1056 words(X16 device) ofdata within the selected page are transferred to the data registers in less than 25µs(tR). The system controller can detect the comple-tion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may beread out in 80ns(1.8V device) or 50ns(3.3V device) cycle time by sequentially pulsing RE. The repetitive high to low transitions of theRE clock make the device output the data starting from the selected column address up to the last column address. The device may output random data in a page instead of the consecutive sequential data by writing random data output command.The column address of next data, which is going to be out, may be changed to the address which follows random data output com-mand. Random data output can be operated multiple times regardless of how many times it is done in a page.Figure 6. Read OperationCLECEWEALER/BREI/Ox00hAddress(5Cycle)Col Add1,2 & Row Add1,2,330hData Output(Serial Access)tRData FieldSpare Field31元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MK9W4G16U1MK9K2G16Q0MK9K2G16U0M
FLASH MEMORY
Figure 7. Random Data Output In a Page
tR
R/BREI/Ox
00h
Address5Cycles
30h
Data Output
05h
Address2Cycles
E0h
Data Output
Data FieldSpare FieldData FieldSpare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytesup to 2112(X8 device) or words up to 1056(X16 device), in a single page program cycle. The number of consecutive partial page pro-gramming operation within the same page without an intervening erase operation must not exceed 4 times for main array(X8device:1time/512byte, X16 device:1time/256word) and 4 times for spare array(X8 device:1time/16byte, X16 device:1time/8word).The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in whichup to 2112bytes(X8 device) or 1056words(X16 device) of data may be loaded into the data register, followed by a non-volatile pro-gramming period where the loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs andthen serial data loading. The bytes other than those to be programmed do not need to be loaded. The device supports random datainput in a page. The column address for the next data, which will be entered, may be changed to the address which follows randomdata input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering theserial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and tim-ings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, theRead Status Register command may be entered to read the status register. The system controller can detect the completion of a pro-gram cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Resetcommand are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may bechecked(Figure 8). The internal write verify detects only errors for \"1\"s that are not successfully programmed to \"0\"s. The commandregister remains in Read Status command mode until another valid command is written to the command register.
Figure 8. Program & Read Status Operation
R/BI/Ox
80h
Address & Data InputCol Add1,2 & Row Add1,2,3
Data
Fail
tPROG
\"0\"
10h
70h
I/O0
\"1\"Pass
32
元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MK9W4G16U1MK9K2G16Q0MK9K2G16U0M
FLASH MEMORY
Figure 9. Random Data Input In a Page
R/BI/Ox
80h
Address & Data InputCol Add1,2 & Row Add1,2,3
Data
Address & Data Input
Col Add1,2 Data
Fail
tPROG
\"0\"
85h
10h
70h
I/O0
\"1\"
Pass
Cache Program
Cache Program is an extension of Page Program, which is executed with 2112byte(X8 device) or 1056word(X16 device) data regis-ters, and is available only within a block. Since the device has 1 page of cache memory, serial data input may be executed while datastored in data register are programmed into memory cell.
After writing the first set of data up to 2112byte(X8 device) or 1056word(X16 device) into the selected cache registers, Cache Pro-gram command (15h) instead of actual Page Program (10h) is inputted to make cache registers free and to start internal programoperation. To transfer data from cache registers to data registers, the device remains in Busy state for a short period of time(tCBSY)and has its cache registers ready for the next data-input while the internal programming gets started with the data loaded into dataregisters. Read Status command (70h) may be issued to find out when cache registers become ready by polling the Cache-Busy sta-tus bit(I/O 6). Pass/fail status of only the previouse page is available upon the return to Ready state. When the next set of data isinputted with the Cache Program command, tCBSY is affected by the progress of pending internal programming. The programming ofthe cache registers is initiated only when the pending program cycle is finished and the data registers are available for the transfer ofdata from cache registers. The status bit(I/O5) for internal Ready/Busy may be polled to identify the completion of internal program-ming. If the system monitors the progress of programming only with R/B, the last page of the target programming sequence must beprogammed with actual Page Program command (10h).
Figure 10. Cache Program (available only within a block)
R/B
80h
Address & Data Input*
tCBSYtCBSYtCBSY
tPROG
15h80h
Address & Data Input
15h
80h
Address & Data Input
15h
80h
Col Add1,2 & Row Add1,2,3
DataCol Add1,2 & Row Add1,2,3
Data
Col Add1,2 & Row Add1,2,3
Data
Address &10h Data Input
Col Add1,2 & Row Add1,2,3
Data
70h
33
元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MK9W4G16U1MK9K2G16Q0MK9K2G16U0M
FLASH MEMORY
NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program. However, ifthe previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after com-pletion of the previous cycle, which can be expressed as the following formula.
tPROG= Program time for the last page+ Program time for the ( last -1 )th page - (Program command cycle time + Last page data loading time)
Copy-Back Program
The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory.Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The ben-efit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assignedfree block. The operation for performing a copy-back program is a sequential execution of page-read without serial access and copy-ing-program with the address of destination page. A read operation with \"35h\" command and the address of the source page movesthe whole 2112byte(X8 device) or 1056word(X16 device) data into the internal data buffer. As soon as the device returns to Readystate, Page-Copy Data-input command (85h) with the address cycles of destination page followed may be written. The Program Con-firm command (10h) is required to actually begin the programming operation. Copy-Back Program operation is allowed only withinthe same memory plane. Once the Copy-Back Program is finished, any additional partial page programming into the copied pages isprohibited before erase. A27 must be the same between source and target page. Data input cycle for modifying a portion or multipledistant portions of the source page is allowed as shown in Figure 12. \"When there is a program-failure at Copy-Back operation,error is reported by pass/fail status. But if the soure page has a bit error for charge loss, accumulated copy-back operationscould also accumulate bit errors. For this reason, two bit ECC is recommended for copy-back operation. \"
Figure 11. Page Copy-Back program Operation
R/BI/Ox
00h
Add.(5Cycles)
35h
tRtPROG
85hAdd.(5Cycles) 10h70hI/O0Pass
Col. Add1,2 & Row Add1,2,3
Source AddressCol. Add1,2 & Row Add1,2,3Destination AddressFail
Figure 12. Page Copy-Back program Operation with Random Data Input
R/BI/Ox
00h
Add.(5Cycles)
35h
tR
tPROG
85hAdd.(5Cycles) Data85h
Add.(2Cycles) Col Add1,2
Data10h70h
Col. Add1,2 & Row Add1,2,3
Source Address
Col. Add1,2 & Row Add1,2,3Destination Address There is no limitation for the number of repetition.34
元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0M
BLOCK ERASE
K9W4G16U1MK9K2G16Q0MK9K2G16U0M
FLASH MEMORY
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup com-mand(60h). Only address A18 to A28(X8) or A17 to A27(X16) is valid while A12 to A17(X8) or A11 to A16(X16) is ignored. The EraseConfirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setupfollowed by execution command ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. Whenthe erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.
Figure 13. Block Erase Operation
R/BI/Ox
60h
tBERS
\"0\"
Address Input(3Cycle)Block Add. : A12 ~ A28 (X8) or A11 ~ A27 (X16)
Fail
D0h
70h
I/O0
\"1\"
Pass
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whetherthe program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputsthe content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allowsthe system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CEdoes not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command registerremains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random readcycle, the read command(00h) should be given before starting read cycles.
Table2. Read Staus Register Definition
I/O No.I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7I/O 8~15
(X16 device
only)
Page ProgramPass/FailNot useNot useNot UseNot UseReady/BusyReady/BusyWrite ProtectNot use
Block ErasePass/FailNot useNot useNot UseNot UseReady/BusyReady/BusyWrite ProtectNot use
Cache ProrgamPass/Fail(N)Pass/Fail(N-1)Not useNot UseNot UseTrue Ready/BusyReady/BusyWrite ProtectNot use
ReadNot useNot useNot useNot UseNot UseReady/BusyReady/BusyWrite ProtectNot use
Definition
Pass : \"0\" Fail : \"1\"Pass : \"0\" Fail : \"1\"Don’t -caredDon’t -caredDon’t -cared
Busy : \"0\" Ready : \"1\"Busy : \"0\" Ready : \"1\"Protected : \"0\" Not Protected Don’t -care
NOTE : 1. True Ready/Busy represents internal program operation status which is being executed in cache program mode. 2. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
35
元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MRead IDK9W4G16U1MK9K2G16Q0MK9K2G16U0MFLASH MEMORYThe device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and XXh, 4th cycle ID, 44h respectively.The command register remains in Read ID mode until further commands are issued to it. Figure 14 shows the operation sequence.Figure 14. Read ID Operation CLECEWEtAR1ALEREI/OXtWHR90h00hAddress. 1cycletCLRtCEAtREAEChMaker codeDeviceCode*Device codeXXh4th Cyc.*DeviceK9K2G08Q0MK9K2G08U0MK9K2G16Q0MK9K2G16U0MK9W4G08U1MK9W4G16U1MDevice Code*(2nd Cycle)AAhDAhBAhCAh4th Cycle*15h15h55h55hSame as each K9K2G08U0M in itSame as each K9K2G16U0M in itRESETThe device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during randomread, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are nolonger valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, andthe Status Register is cleared to value C0h when WP is high. Refer to table 3 for device status after reset operation. If the device isalready in reset state a new reset command will be accepted by the command register. The R/B pin transitions to low for tRST afterthe Reset command is written. Refer to Figure 15 below.Figure 15. RESET OperationR/BI/OXFFhtRSTTable3. Device StatusAfter Power-upPRE statusOperation ModeHighFirst page data access is readyLow00h command is latchedAfter ResetWaiting for next command36元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MK9W4G16U1MK9K2G16Q0MK9K2G16U0MFLASH MEMORYPower-On Auto-ReadThe device is designed to offer automatic reading of the first page without command and address input sequence during power-on.An internal voltage detector enables auto-page read functions when Vcc reaches about 1.8V. PRE pin controls activation of auto-page read function. Auto-page read function is enabled only when PRE pin is tied to Vcc. Serial access may be done after power-onwithout latency. Power-On Auto Read mode is available only on 3.3V device(K9XXGXXUXM).Figure 16. Power-On Auto-Read (3.3V device only)~ 1.8VVCCWEALEPRER/BtRREI/OX1st2nd3rd≈....≈n th37≈≈≈≈≈CE≈CLE≈元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MREADY/BUSYK9W4G16U1MK9K2G16Q0MK9K2G16U0MFLASH MEMORYThe device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and randomread completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis-ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin isan open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) andcurrent drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 17). Its value can bedetermined by the following guidance.RpVCCibusy1.8V device - VOL : 0.1V, VOH : VCCq-0.1V3.3V device - VOL : 0.4V, VOH : 2.4VReady VccR/Bopen drain outputVOHCL VOLBusytftrGNDDeviceFigure 17. Rp vs tr ,tf & Rp vs ibusy@ Vcc = 1.8V, Ta = 25°C , CL = 30pF2.4@ Vcc = 3.3V, Ta = 25°C , CL = 100pF400tr,tf [s]300nIbusy3mIbusy [A]tr,tf [s]300nIbusy1.22003003mIbusy [A]200n100n1.72mtr0.8560900.571.7120200ntr100n1003.60.80.62m1m301.70.431.71mtf1.7tf3.63.63.61K2K3KRp(ohm)4K1K2K3KRp(ohm)4KRp value guidanceVCC(Max.) - VOL(Max.) IOL + ΣILVCC(Max.) - VOL(Max.) IOL + ΣIL = =1.85V3mA + ΣIL3.2V8mA + ΣILRp(min, 1.8V part) =Rp(min, 3.3V part) =where IL is the sum of the input currents of all devices tied to the R/B pin.Rp(max) is determined by maximum permissible limit of tr 38元器件交易网www.cecb2b.com
K9W4G08U1MK9K2G08Q0MK9K2G08U0MK9W4G16U1MK9K2G16Q0MK9K2G16U0M
FLASH MEMORY
Data Protection & Power up sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detectordisables all functions whenever Vcc is below about 1.1V(1.8V device) or 2V(3.3V device). WP pin provides hardware protection andis recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10µs is required before internal cir-cuit gets ready for any command sequences as shown in Figure 18. The two step command sequence for program/erase providesadditional software protection.
Figure 18. AC Waveforms for Power Transition
1.8V device : ~ 1.5V3.3V device : ~ 2.5V
VCC
High
≈1.8V device : ~ 1.5V3.3V device : ~ 2.5V
WP
WE
39
≈10µs
≈≈
因篇幅问题不能全部显示，请点此查看更多更全内容