MOTOROLASEMICONDUCTOR TECHNICAL DATAB-Suffix Series CMOS GatesThe B Series logic gates are constructed with P and N channelenhancement mode devices in a single monolithic structure (Complemen-tary MOS). Their primary use is where low power dissipation and/or highnoise immunity is desired.•Supply Voltage Range = 3.0 Vdc to 18 Vdc•All Outputs Buffered•Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range.•Double Diode Protection on All Inputs Except: Triple Diode Protectionon MC14011B and MC14081B•Pin–for–Pin Replacements for Corresponding CD4000 Series B SuffixDevices (Exceptions: MC14068B and MC14078B)Quad 2-Input NOR GateDual 4-Input NOR GateQuad 2-Input NAND GateDual 4-Input NAND GateTriple 3-Input NAND GateTriple 3-Input NOR Gate8-Input NAND GateQuad 2-Input OR GateDual 4-Input OR GateTriple 3-Input AND GateTriple 3-Input OR Gate8-Input NOR GateQuad 2-Input AND GateDual 4-Input AND GateMC14001BMC14002BMC14011BMC14012BMC14023BMC14025BMC14068BMC14071BMC14072BMC14073BMC14075BMC14078BMC14081BMC14082BL SUFFIXCERAMICCASE 632P SUFFIXPLASTICCASE 646D SUFFIXSOICCASE 751AORDERING INFORMATIONMC14XXXBCPMC14XXXBCLMC14XXXBDPlasticCeramicSOICTA = – 55° to 125°C for all packages.MAXIMUM RATINGS* (Voltages Referenced to VSS)SymbolVDDParameterDC Supply VoltageValueUnitVV– 0.5 to + 18.0Vin, Voutlin, loutPDInput or Output Voltage (DC or Transient)– 0.5 to VDD + 0.5± 10500Input or Output Current (DC or Transient),per PinPower Dissipation, per Package†Storage TemperaturemAmW_CTstg– 65 to + 150TLLead Temperature (8–Second Soldering)260_C*Maximum Ratings are those values beyond which damage to the device may occur.†Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_CCeramic “L” Packages: – 12 mW/_C From 100_C To 125_CThis device contains protection circuitry to guard against damagedue to high static voltages or electric fields. However, precautions mustbe taken to avoid applications of any voltage higher than maximum ratedvoltages to this high-impedance circuit. For proper operation, Vin andVout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.Unused inputs must always be tied to an appropriate logic voltagelevel (e.g., either VSS or VDD). Unused outputs must be left open.REV 31/94©MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995MC14001B7元器件交易网www.cecb2b.com
LOGIC DIAGRAMSNORMC14001BQuad 2–Input NOR Gate12NANDMC14011BQuad 2–Input NAND Gate1256891213ORMC14071BQuad 2–Input OR Gate1256891213ANDMC14081BQuad 2–Input AND Gate125689121333332 INPUT5689121344441010101011111111MC14025BTriple 3–Input NOR Gate1283451112139MC14023BTriple 3–Input NAND Gate1283451112139MC14075BTriple 3–Input OR Gate1283451112139MC14073BTriple 3–Input AND Gate12834511121393 INPUT666610101010MC14002BDual 4–Input NOR Gate23459101112MC14012BDual 4–Input NAND Gate23459101112MC14072BDual 4–Input OR Gate23459101112MC14082BDual 4–Input AND Gate234591011124 INPUT111113NC = 6, 813NC = 6, 813NC = 6, 813NC = 6, 8MC14078B8–Input NOR Gate2345910111223459101112MC14068B8–Input NAND GateVDD = PIN 14VSS = PIN 7FOR ALL DEVICES138 INPUT13NC = 6, 8NC = 6, 8MC14001B8MOTOROLA CMOS LOGIC DATA元器件交易网www.cecb2b.com
PIN ASSIGNMENTSMC14001BQuad 2–Input NOR GateIN 1AIN 2AOUTAOUTBIN 1BIN 2BVSS1234567141312111098VDDIN 2DIN 1DOUTDOUTCIN 2CIN 1CMC14002BDual 4–Input NOR GateOUTAIN 1AIN 2AIN 3AIN 4ANCVSS1234567141312111098VDDOUTBIN 4BIN 3BIN 2BIN 1BNCMC14011BQuad 2–Input NAND GateIN 1AIN 2AOUTAOUTBIN 1BIN 2BVSS1234567141312111098VDDIN 2DIN 1DOUTDOUTCIN 2CIN 1CMC14012BDual 4–Input NAND GateOUTAIN 1AIN 2AIN 3AIN 4ANCVSS1234567141312111098VDDOUTBIN 4BIN 3BIN 2BIN 1BNCMC14023BTriple 3–Input NAND GateIN 1AIN 2AIN 1BIN 2BIN 3BOUTBVSS1234567141312111098VDDIN 3CIN 2CIN 1COUTCOUTAIN 3AMC14025BTriple 3–Input NOR GateIN 1AIN 2AIN 1BIN 2BIN 3BOUTBVSS1234567141312111098VDDIN 3CIN 2CIN 1COUTCOUTAIN 3AMC14068B8–Input NAND GateNCIN 1IN 2IN 3IN 4NCVSS1234567141312111098VDDOUTIN 8IN 7IN 6IN 5NCMC14071BQuad 2–Input OR GateIN 1AIN 2AOUTAOUTBIN 1BIN 2BVSS1234567141312111098VDDIN 2DIN 1DOUTDOUTCIN 2CIN 1CMC14072BDual 4–Input OR GateOUTAIN 1AIN 2AIN 3AIN 4ANCVSS1234567141312111098VDDOUTBIN 4BIN 3BIN 2BIN 1BNCMC14073BTriple 3–Input AND GateIN 1AIN 2AIN 1BIN 2BIN 3BOUTBVSS1234567141312111098VDDIN 3CIN 2CIN 1COUTCOUTAIN 3AMC14075BTriple 3–Input OR GateIN 1AIN 2AIN 1BIN 2BIN 3BOUTBVSS1234567141312111098VDDIN 3CIN 2CIN 1COUTCOUTAIN 3AMC14078B8–Input NOR GateNCIN 1IN 2IN 3IN 4NCVSS1234567141312111098VDDOUTIN 8IN 7IN 6IN 5NCMC14081BQuad 2–Input AND GateIN 1AIN 2AOUTAOUTBIN 1BIN 2BVSS1234567141312111098VDDIN 2DIN 1DOUTDOUTCIN 2CIN 1CMC14082BDual 4–Input AND GateOUTAIN 1AIN 2AIN 3AIN 4ANCVSS1234567141312111098VDDOUTBIN 4BIN 3BIN 2BIN 1BNCNC = NO CONNECTIONMOTOROLA CMOS LOGIC DATAMC14001B9元器件交易网www.cecb2b.com
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)CharacteristicSymbolVOLVDDVdc5.010155.010155.010155.010155.05.010155.0101515—5.010155.01015Min———– 55_C25_C125_CMaxMin———Typ #000MaxMin———MaxUnitVdcOutput VoltageVin = VDD or 0“0” Level0.050.050.05———0.050.050.05———0.050.050.05———“1” LevelVin = 0 or VDDVOH4.959.9514.95———4.959.9514.95———5.010154.959.9514.95———VdcInput Voltage“0” Level(VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)“1” Level(VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)VILVdc1.53.04.0——————————2.254.506.752.755.508.251.53.04.0——————————1.53.04.0——————————VIHVdc3.57.0113.57.0113.57.011Output Drive Current(VOH = 2.5 Vdc) (VOH = 4.6 Vdc)(VOH = 9.5 Vdc)(VOH = 13.5 Vdc)(VOL = 0.4 Vdc) (VOL = 0.5 Vdc)(VOL = 1.5 Vdc)SourceIOHmAdc– 3.0– 0.64– 1.6– 4.20.641.64.2—————– 2.4– 0.51– 1.3– 3.40.511.33.4—————– 4.2– 0.88 – 2.25– 8.80.882.258.8– 1.7– 0.36– 0.9– 2.40.360.92.4—————SinkIOLmAdcInput CurrentInput Capacitance(Vin = 0)IinCinIDD± 0.1—0.250.51.0±0.000015.00.00050.00100.0015± 0.17.50.250.51.0± 1.0—7.51530µAdcpFµAdcQuiescent Current(Per Package)Total Supply Current**†(Dynamic plus Quiescent,Per Gate, CL = 50 pF)ITIT = (0.3 µA/kHz) f + IDD/NIT = (0.6 µA/kHz) f + IDD/NIT = (0.9 µA/kHz) f + IDD/NµAdc#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.**The formulas given are for the typical characteristics only at 25_C.†To calculate total supply current at loads other than 50 pF:IT(CL) = IT(50 pF) + (CL – 50) Vfkwhere: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates perpackage.MC14001B10MOTOROLA CMOS LOGIC DATA元器件交易网www.cecb2b.com
B–SERIES GATE SWITCHING TIMESSWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)CharacteristicSymboltTLHVDDVdc5.010155.01015Min——————Typ #10050401005040Max2001008020010080UnitnsOutput Rise Time, All B–Series GatestTLH = (1.35 ns/pF) CL + 33 nstTLH = (0.60 ns/pF) CL + 20 nstTLH = (0.40 ns/PF) CL + 20 nsOutput Fall Time, All B–Series GatestTHL = (1.35 ns/pF) CL + 33 nstTHL = (0.60 ns/pF) CL + 20 nstTHL = (0.40 ns/pF) CL + 20 nstTHLnsPropagation Delay TimeMC14001B, MC14011B onlytPLH, tPHL = (0.90 ns/pF) CL + 80 nstPLH, tPHL = (0.36 ns/pF) CL + 32 nstPLH, tPHL = (0.26 ns/pF) CL + 27 nsAll Other 2, 3, and 4 Input GatestPLH, tPHL = (0.90 ns/pF) CL + 115 nstPLH, tPHL = (0.36 ns/pF) CL + 47 nstPLH, tPHL = (0.26 ns/pF) CL + 37 ns8–Input Gates (MC14068B, MC14078B)tPLH, tPHL = (0.90 ns/pF) CL + 155 nstPLH, tPHL = (0.36 ns/pF) CL + 62 nstPLH, tPHL = (0.26 ns/pF) CL + 47 nstPLH, tPHL5.010155.010155.01015—————————12550401606550200806025010080300130100350150110ns*The formulas given are for the typical characteristics only at 25_C.#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.14PULSEGENERATORINPUTVDD20 nsINPUTOUTPUTtPHLOUTPUTINVERTING90%50%10%tTHLtPLH90%50%10%20 nsVDD0 VtPLHVOHtTLHtPHL90%50%10%VOLVOHVOL*CL7VSS*All unused inputs of AND, NAND gates must be connected to VDD.All unused inputs of OR, NOR gates must be connected to VSS.OUTPUTNON–INVERTINGtTLHtTHLFigure 1. Switching Time Test Circuit and WaveformsMOTOROLA CMOS LOGIC DATAMC14001B11元器件交易网www.cecb2b.com
CIRCUIT SCHEMATICNOR, OR GATESMC14001B, MC14071BOne of Four Gates ShownVDD1, 6, 8, 13*2, 5, 9, 123, 4, 10, 1114VDDMC14025B, MC14075BOne of Three Gates ShownVSS*Inverter omitted in MC14001B7VSS1, 3, 112, 4, 1214*VDDVDDMC14002B, MC14072BOne of Two Gates ShownVDD3, 92, 1014*VDD8, 5, 13VSSVDD9, 6, 107VSSVSS*Inverter omitted in MC14025BVSS1, 135, 114, 12SAME ASABOVE*Inverter omitted in MC14002B7VSSVDD23MC14078BEight Input Gate14VSSSAME ASABOVESAME ASABOVESAME ASABOVEVDD459101112137VSSMC14001B12MOTOROLA CMOS LOGIC DATA元器件交易网www.cecb2b.com
CIRCUIT SCHEMATICNAND, AND GATESMC14011B, MC14081BOne of Four Gates Shown14*VDDMC14023B, MC14073BOne of Three Gates ShownVDD2, 5, 9, 121, 6, 8, 133, 4, 10, 117VSS*Inverter omitted in MC14011B2, 4, 121, 3, 1114VDDVSSVDD*9, 6, 108, 5, 137*Inverter omitted in MC14023BVSSMC14012B, MC14082BOne of Two Gates ShownVDDVSSVDDMC14068BEight Input Gate142, 103, 9VSS4, 125, 11SAME ASABOVE*Inverter omitted in MC14012B7*VDD1, 13VDD23VSSSAME ASABOVEVSS5414VSS9101112SAME ASABOVESAME ASABOVEVDDVDD137VSSVSSMOTOROLA CMOS LOGIC DATAMC14001B13元器件交易网www.cecb2b.com
TYPICAL B–SERIES GATE CHARACTERISTICSN–CHANNEL DRAIN CURRENT(SINK)5.0– 10– 9.0I ,DRAIN CURRENT (mA)DI ,DRAIN CURRENT (mA)D4.03.0TA = – 55°C– 40°C+ 85°C+ 25°C+ 125°C– 8.0– 7.0– 6.0– 5.0– 4.0– 3.0– 2.0– 1.0001.02.03.04.0VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)5.000– 1.0– 2.0– 3.0– 4.0VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)– 5.0+ 85°C– 40°C+ 25°CTA = – 55°CP–CHANNEL DRAIN CURRENT(SOURCE)2.01.0+ 125°CFigure 2. VGS = 5.0 Vdc2018I ,DRAIN CURRENT (mA)D161412108.06.04.02.0001.02.03.04.05.06.07.08.0VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)9.010TA = – 55°C– 40°C+ 25°C+ 85°C+ 125°C– 50– 45I ,DRAIN CURRENT (mA)D– 40– 35– 30– 25– 20– 15– 10– 5.000Figure 3. VGS = – 5.0 VdcTA = – 55°C+ 25°C– 40°C+ 85°C+ 125°C– 1.0– 2.0– 3.0– 4.0– 5.0– 6.0– 7.0– 8.0– 9.0– 10VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)Figure 4. VGS = 10 Vdc504540I ,DRAIN CURRENT (mA)D3530252015105.0002.04.06.08.010121416VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)1820+ 125°CTA = – 55°C– 40°C+ 25°C+ 85°CI ,DRAIN CURRENT (mA)D– 100– 90– 80– 70– 60– 50– 40– 30– 20– 1000Figure 5. VGS = – 10 VdcTA = – 55°C– 40°C+ 25°C+ 85°C+ 125°C– 2.0– 4.0– 6.0– 8.0– 10– 12– 14– 16VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)– 18– 20Figure 6. VGS = 15 VdcFigure 7. VGS = – 15 VdcThese typical curves are not guarantees, but are design aids.Caution: The maximum rating for output current is 10 mA per pin.MC14001B14MOTOROLA CMOS LOGIC DATA元器件交易网www.cecb2b.com
TYPICAL B–SERIES GATE CHARACTERISTICS (cont’d)VOLTAGE TRANSFER CHARACTERISTICSV o u t ,OUTPUT VOLTAGE (Vdc)5.04.03.02.01.0001.02.0SINGLE INPUT NAND, ANDMULTIPLE INPUT NOR, ORV o u t ,OUTPUT VOLTAGE (Vdc)108.06.04.02.0002.04.0SINGLE INPUT NAND, ANDMULTIPLE INPUT NOR, ORSINGLE INPUT NOR, ORMULTIPLE INPUT NAND, ANDSINGLE INPUT NOR, ORMULTIPLE INPUT NAND, AND3.04.05.0Vin, INPUT VOLTAGE (Vdc)6.08.010Vin, INPUT VOLTAGE (Vdc)Figure 8. VDD = 5.0 VdcFigure 9. VDD = 10 Vdc16V o u t ,OUTPUT VOLTAGE (Vdc)1412108.06.04.02.0002.04.06.08.010Vin, INPUT VOLTAGE (Vdc)SINGLE INPUT NOR, ORMULTIPLE INPUT NAND, ANDSINGLE INPUT NAND, ANDMULTIPLE INPUT NOR, ORDC NOISE MARGINThe DC noise margin is defined as the input voltage rangefrom an ideal “1” or “0” input level which does not produceoutput state change(s). The typical and guaranteed limit val-ues of the input values VIL and VIH for the output(s) to be at afixed voltage VO are given in the Electrical Characteristicstable. VIL and VIH are presented graphically in Figure 11.Guaranteed minimum noise margins for both the “1” and“0” levels =1.0 V with a 5.0 V supply2.0 V with a 10.0 V supply2.5 V with a 15.0 V supplyFigure 10. VDD = 15 VdcVoutVOVDDVoutVOVDDVOVDD0VILVIHVinVOVDD0VILVSS = 0 VOLTS DCVIHVin(a) Inverting Function(b) Non–Inverting FunctionFigure 11. DC Noise ImmunityMOTOROLA CMOS LOGIC DATAMC14001B15元器件交易网www.cecb2b.com
OUTLINE DIMENSIONSL SUFFIXCERAMIC DIP PACKAGECASE 632–08ISSUE Y9NOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.DIMENSION L TO CENTER OF LEAD WHENFORMED PARALLEL.4.DIMENSION F MAY NARROW TO 0.76 (0.030)WHERE THE LEAD ENTERS THE CERAMICBODY.INCHESMINMAX0.7500.7850.2450.2800.1550.2000.0150.0200.0550.0650.100 BSC0.0080.0150.1250.1700.300 BSC0 _15 _0.0200.040MILLIMETERSMINMAX19.0519.946.237.113.945.080.390.501.401.652.54 BSC0.210.383.184.317.62 BSC0 _15 _0.511.01–A–14–B–17CL–T–SEATINGPLANEKFD14 PLG0.25 (0.010)MNJTAS14 PLM0.25 (0.010)MTBSDIMABCDFGJKLMNP SUFFIXPLASTIC DIP PACKAGECASE 646–06ISSUE L148B17NOTES:1.LEADS WITHIN 0.13 (0.005) RADIUS OF TRUEPOSITION AT SEATING PLANE AT MAXIMUMMATERIAL CONDITION.2.DIMENSION L TO CENTER OF LEADS WHENFORMED PARALLEL.3.DIMENSION B DOES NOT INCLUDE MOLDFLASH.4.ROUNDED CORNERS OPTIONAL.DIMABCDFGHJKLMNINCHESMINMAX0.7150.7700.2400.2600.1450.1850.0150.0210.0400.0700.100 BSC0.0520.0950.0080.0150.1150.1350.300 BSC0 10 __0.0150.039MILLIMETERSMINMAX18.1619.566.106.603.694.690.380.531.021.782.54 BSC1.322.410.200.382.923.437.62 BSC0 _10 _0.391.01AFCNHGDSEATINGPLANELJKMMC14001B16MOTOROLA CMOS LOGIC DATA元器件交易网www.cecb2b.com
OUTLINE DIMENSIONSD SUFFIXPLASTIC SOIC PACKAGECASE 751A–03ISSUE F–A–148–B–17P7 PL0.25 (0.010)MBMNOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS A AND B DO NOT INCLUDEMOLD PROTRUSION.4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.5.DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.GC–T–SEATINGPLANERX 45_FD14 PL0.25 (0.010)MKTBSMASJDIMABCDFGJKMPRMILLIMETERSMINMAX8.558.753.804.001.351.750.350.490.401.251.27 BSC0.190.250.100.250 7 __5.806.200.250.50INCHESMINMAX0.3370.3440.1500.1570.0540.0680.0140.0190.0160.0490.050 BSC0.0080.0090.0040.0090 7 __0.2280.2440.0100.019How to reach us:
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MOTOROLA CMOS LOGIC DATA
MC14001B
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