Clock recovery circuit

专利名称：Clock recovery circuit

发明人：Salomon Serfaty,Mordechay Cohen申请号：US06/619666申请日：19840611公开号：US04651026A公开日：19870317

摘要：The invention provides a clock recovery circuit for deriving a recovered clocksignal from the band limited multi-level digital signal. The multi-level digital signal iscompared with a number of reference levels in a bank of comparators whose outputs arecombined to provide a marking signal indicative of threshold crossings by the multi-levelsignal. The marking signal consists of groups of transition markers separated by eyeintervals. A signal source provides clock pulses and window pulses with the windowpulses being synchronized with the eye intervals to provide a recovered clock signal.

The invention may be implemented entirely in digital form and is particularly suitablefor use in partial response signalling in which band limited multi-level digital signals aretransmitted without additional clock signals. Performance may be further enhanced byutilizing a smoothing phase locked loop to provide a smoothed clock signal.

申请人：MOTOROLA, INC.

代理人：Donald B. Southard,Charles L. Warren

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