DS25BR150 3.125 Gbps LVDS BufferApril 2007
DS25BR150
3.125 Gbps LVDS Buffer
General Description
The DS25BR150 is a single channel 3.125 Gbps LVDS bufferoptimized for high-speed signal transmission over printed cir-cuit boards and balanced cables. Fully differential signalpaths ensure exceptional signal integrity and noise immunity.The DS25BR150 is a buffer/repeater with very low powerconsumption. Other LVDS devices with similar IO character-istics and with signal conditioning features include the follow-ing products. The DS25BR110 features four levels ofequalization for use as an optimized receiver device, theDS25BR120 features four levels of pre-emphasis for use asan optimized driver device, while the DS25BR100 featuresboth pre-emphasis and equalization for use as an optimizedrepeater device.
Wide input common mode range allows the receiver to acceptsignals with LVDS, CML and LVPECL levels; the output levelsare LVDS. A very small package footprint requires a minimalspace on the board while the flow-through pinout allows easyboard layout. The differential inputs and outputs are internallyterminated with a 100Ω resistor to lower device input and out-put return losses, reduce component count, and further min-imize board space.
Features
■DC - 3.125 Gbps low jitter, high noise immunity, low power
operation
■On-chip 100 Ω input and output termination minimizesinsertion and return losses, reduces component count andminimizes board space
■7 kV ESD on LVDS I/O pins protects adjoiningcomponents
■Small 3 mm x 3 mm LLP-8 space saving package
Applications
■■■■■■■
Clock or data buffering / repeating
OC-48 / STM-16 Clock or data buffering / repeatingSerial ATA (SATA-150 and SATA-300)Fibre Channel (2GFC)PCI ExpressInfiniBandFireWire
Typical Application
30005510
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DS25BR150Block Diagram
30005507
Pin Diagram
30005508
Pin Descriptions
Pin NameNCIN+IN-NCNCOUT-OUT+VCCGND
Pin Name12345678DAP
Pin TypeNAInputInputNANAOutputOutputPowerPower
Pin Description\"NO CONNECT\" pin.Non-inverting LVDS input pin.Inverting LVDS input pin.\"NO CONNECT\" pin.\"NO CONNECT\" pin.Inverting LVDS output pin.Non-inverting LVDS Output pin.Power supply pin.
Ground pad (DAP - die attach pad)
Ordering Codes and Configurations
NSID
DS25BR150TSD
FunctionBuffer/Repeater
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DS25BR150Absolute Maximum Ratings (Note 4)
If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage (VCC)−0.3V to +4VLVDS Input Voltage (IN+, IN−)−0.3V to +4VLVDS Differential Input Voltage ((IN+) - (IN−))0V to 1VLVDS Output Voltage (OUT+,OUT−)−0.3V to +4VLVDS Differential Output Voltage ((OUT+) - (OUT−))0V to 1VLVDS Output Short Circuit Current
5 ms
Duration
Junction Temperature+150°CStorage Temperature Range−65°C to +150°CLead Temperature Range Soldering (4 sec.)+260°CMaximum Package Power Dissipation at 25°C SDA Package2.08W Derate SDA Package16.7 mW/°C above +25°C
Package Thermal Resistance θJA
θJC
ESD Susceptibility HBM (Note 1) MM (Note 2) CDM (Note 3)
Note 1:Human Body Model, applicable std. JESD22-A114CNote 2:Machine Model, applicable std. JESD22-A115-ANote 3:Field Induced Charge Device Model, applicable std.JESD22-C101-C
+60.0°C/W+12.3°C/W
≥7 kV≥250V≥1250V
Recommended OperatingConditions
Supply Voltage (VCC)
Receiver Differential InputVoltage (VID)
Operating Free AirTemperature (TA)
Min3.00−40
Typ3.3 +25
Max3.61+85
UnitsVV°C
DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 5, 6, 7)SymbolVODΔVODVOSΔVOSIOSCOUTROUT
Parameter
Differential Output Voltage
Change in Magnitude of VOD for ComplimentaryOutput StatesOffset Voltage
Change in Magnitude of VOS for ComplimentaryOutput States
Output Short Circuit Current (Note 8)Output CapacitanceOutput Termination Resistor
RL = 100ΩOUT to GNDOUT to VCC
Any LVDS Output Pin to GNDBetween OUT+ and OUT-RL = 100Ω
Conditions
Min250-351.05-35
Typ350 1.2 -257.51.2100
Max450351.37535-5050
UnitsmVmVVmVmAmApFΩ
LVDS OUTPUT DC SPECIFICATIONS (OUT+, OUT-)
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DS25BR150SymbolVIDVTHVTLVCMRIINCINRINICC
Parameter
Input Differential VoltageDifferential Input High ThresholdDifferential Input Low ThresholdCommon Mode Voltage Range
VCM = +0.05V or VCC-0.05V
VID = 100 mVVIN = 3.6V or 0VVCC = 3.6V or 0V
Any LVDS Input Pin to GNDBetween IN+ and IN-
Conditions
Min0 −1000.05
Typ 00 ±11.710027
VCC -0.05±10 35Max1+100
UnitsVmVmVVμApFΩmA
LVDS INPUT DC SPECIFICATIONS (IN+, IN-)
Input CurrentInput CapacitanceInput Termination ResistorSupply Current
SUPPLY CURRENT
Note 4:“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliabilityand/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated inthe Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and thedevice should not be operated beyond such conditions.
Note 5:The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modifiedor specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 6:Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD andΔVOD.
Note 7:Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time ofproduct characterization and are not guaranteed.
Note 8:Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
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DS25BR150AC Electrical Characteristics
SymboltPHLDtPLHDtSKD1tSKD2tLHTtHLTtDJ1tDJ2tRJ1tRJ2tTJ1tTJ2
Parameter
(Note 11)
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 9, 10)
Conditions
Min
2.5 Gbps3.125 Gbps1.25 GHz1.5625 GHz2.5 Gbps3.125 Gbps
Typ3703551545808011150.50.50.040.07
Max5205201001601501503341110.110.15
UnitspspspspspspspspspspsUIP-PUIP-P
LVDS OUTPUT AC SPECIFICATIONS (OUT+, OUT-)
Differential Propagation Delay High to LowDifferential Propagation Delay Low to HighPulse Skew |tPLHD − tPHLD| (Note 12)Part to Part Skew (Note 13)Rise TimeFall Time
RL = 100Ω
RL = 100Ω
JITTER PERFORMANCE (Figure 5)
Deterministic Jitter (Peak-to-Peak Value )(Note 15)
Random Jitter (RMS Value)(Note 14)
Total Jitter (Peak to Peak Value)(Note 16)
VID = 350 mVVCM = 1.2VK28.5 (NRZ)VID = 350 mVVCM = 1.2VClock (RZ)VID = 350 mVVCM = 1.2V
PRBS-23 (NRZ)
Note 9:The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modifiedor specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 10:Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time ofproduct characterization and are not guaranteed.
Note 11:Specification is guaranteed by characterization and is not tested in production.
Note 12:tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge ofthe same channel.
Note 13:tSKD2, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specificationapplies to devices at the same VCC and within 5°C of each other within the operating temperature range.
Note 14:Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.Note 15:Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtractedalgebraically.
Note 16:Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted.
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DS25BR150DC Test Circuits
30005520
FIGURE 1. Differential Driver DC Test Circuit
AC Test Circuits and Timing Diagrams
30005521
FIGURE 2. Differential Driver AC Test Circuit
30005522
FIGURE 3. Propagation Delay Timing Diagram
30005523
FIGURE 4. LVDS Output Transition Times
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DS25BR15030005529
FIGURE 5. Jitter Measurements Test Circuit
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DS25BR150Device Operation
INPUT INTERFACING
The DS25BR150 accepts differential signals and allows simple AC or DC coupling. With a wide common mode range, theDS25BR150 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The following three figures illus-trate typical DC-coupled interface to common differential drivers. Note that the DS25BR150 inputs are internally terminated witha 100Ω resistor.
Typical LVDS Driver DC-Coupled Interface to DS25BR150 Input
30005511
Typical CML Driver DC-Coupled Interface to DS25BR150 Input
30005512
Typical LVPECL Driver DC-Coupled Interface to DS25BR150 Input
30005513
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DS25BR150OUTPUT INTERFACING
The DS25BR150 outputs signals are compliant to the LVDS standard. It can be DC-coupled to most common differential receivers.The following figure illustrates typical DC-coupled interface to common differential receivers and assumes that the receivers havehigh impedance inputs. While most differential receivers have a common mode input range that can accomodate LVDS compliantsignals, it is recommended to check respective receiver's data sheet prior to implementing the suggested interface implementation.
Typical DS25BR150 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
30005514
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DS25BR150Typical Performance
A 2.5 Gbps NRZ PRBS-7 Output Eye Diagram
V:100 mV / DIV, H:75 ps / DIV
30005531
A 3.125 Gbps NRZ PRBS-7 Output Eye Diagram
V:100 mV / DIV, H:50 ps / DIV
30005530
Total Jitter as a Function of Input Amplitude
30005532
Total Jitter as a Function of Input Amplitude
30005533
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DS25BR150Physical Dimensions inches (millimeters) unless otherwise noted
Order Number DS25BR150TSDNS Package Number SDA08A
(See AN-1187 for PCB Design and Assembly Recommendations)
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DS25BR150 3.125 Gbps LVDS BufferI
I
Notes
IIII
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