SN74CBT16245DGGR,SN74CBT16245DGVR,SN74CBT16245DLR,规格书,Datasheet 资料

 SCDS070C – JULY 1998 – REVISED OCTOBER 2000SN74CBT1624516-BIT FET BUS SWITCH DMember of Texas Instruments’ Widebus™DDDDDFamilyStandard ’16245-Type Pinout5-Ω Switch Connection Between Two PortsTTL-Compatible Input LevelsLatch-Up Performance Exceeds 100 mA PerJESD 78, Class IIESD Protection Exceeds JESD 22– 2000-V Human-Body Model (A114-A)– 200-V Machine Model (A115-A)– 1000-V Charged-Device Model (C101)DGG, DGV, OR DL PACKAGE(TOP VIEW)descriptionThe SN74CBT16245 device provides 16 bits ofhigh-speed TTL-compatible bus switching in astandard ’16245 device pinout. The low on-stateresistance of the switch allows connections to bemade with minimal propagation delay.The device is organized as two 8-bit low-impedanceswitches with separate output-enable (OE) inputs.When OE is low, the switch is on, and data canflow from the A port to the B port, or vice versa.When OE is high, the switch is open, and thehigh-impedance state exists between the twoports.NC1B11B2GND1B31B4VCC1B51B6GND1B71B82B12B2GND2B32B4VCC2B52B6GND2B72B8NC1234567891011121314151617181920212223244847464544434241403938373635343332313029282726251OE1A11A2GND1A31A4VCC1A51A6GND1A71A82A12A2GND2A32A4VCC2A52A6GND2A72A82OENC – No internal connectionORDERING INFORMATIONTAPACKAGE†SSOPDLSSOP – DL–4040°CC to 85to85°CTSSOP – DGGTVSOP – DGVTubeTape and reelTape and reelTape and reelORDERABLEPART NUMBERSN74CBT16245DLSN74CBT16245DLRSN74CBT16245DGGRSN74CBT16245DGVRTOP-SIDEMARKINGCBT16245CBT16245CY245†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines areavailable at www.ti.com/sc/package.FUNCTION TABLE(each 8-bit bus switch)INPUTOELHFUNCTIONA port = B portDisconnectPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Widebus is a trademark of Texas Instruments.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright © 2000, Texas Instruments IncorporatedPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•1芯天下--http://oneic.com/SCDS070C – JULY 1998 – REVISED OCTOBER 2000SN74CBT1624516-BIT FET BUS SWITCH logic diagram (positive logic)1A14721B11A837121B8481OE2A136132B12A826232B82OE25absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 VInput voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 VContinuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mAInput clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mAPackage thermal impedance, θJA (see Note 2):DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/WDGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/WDL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°CStorage temperature range, Tstg –65†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTES:1.The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.2.The package thermal impedance is calculated in accordance with JESD 51-7.recommended operating conditions (see Note 3)MINVCCVIHVILTASupply voltageHigh-level control input voltageLow-level control input voltageOperating free-air temperature–40420.885MAX5.5UNITVVV°CNOTE 3:All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.2POST OFFICE BOX 655303 DALLAS, TEXAS 75265•芯天下--http://oneic.com/ SCDS070C – JULY 1998 – REVISED OCTOBER 2000SN74CBT1624516-BIT FET BUS SWITCH electrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)PARAMETERVIKIIICC∆ICC‡CiCio(OFF)VCC = 4.5 V,VCC = 0,VCC = 5.5 V,VCC = 5.5 V,Control inputsControl inputsVCC = 5.5 V,VI = 3 V or 0VO = 3 V or 0,VCC = 4 V,TYP at VCC = 4 VVCC = 4.5 VTEST CONDITIONSII = –18 mAVI = 5.5 VVI = 5.5 V or GNDIO = 0,One input at 3.4 V,OE = VCCVI = 2.4 V,=0VI = 0II = 15 mAII = 64 mAII = 30 mAVI = VCC or GNDOther inputs at VCC or GND3.54.514552077ΩMINTYP†MAX–1.210±132.5UNITVµAµAmApFpFron§VI = 2.4 V,II = 15 mA812†All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.‡This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.§Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined bythe lower of the voltages of the two (A or B) terminals.switching characteristics over recommended operating free-air temperature range (unlessotherwise noted) (see Figure 1)PARAMETERtpd¶tentdisFROM(INPUT)A or BOEOETO(OUTPUT)B or AA or BA or BVCC = 4 VMINMAX0.356.17.51.23.9VCC = 5 V± 0.5 VMINMAX0.255.67.7nsnsnsUNIT¶The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, whendriven by an ideal voltage source (zero output impedance).POST OFFICE BOX 655303 DALLAS, TEXAS 75265•3芯天下--http://oneic.com/SCDS070C – JULY 1998 – REVISED OCTOBER 2000SN74CBT1624516-BIT FET BUS SWITCH PARAMETER MEASUREMENT INFORMATION7 VFrom OutputUnder TestCL = 50 pF(see Note A)500 ΩS1OpenGND500 Ω3 VLOAD CIRCUITOutputControl1.5 V1.5 V0 VtPZL3 VInput1.5 V1.5 V0 VtPLHOutput1.5 VVOLTAGE WAVEFORMSPROPAGATION DELAY TIMEStPHLVOH1.5 VVOLOutputWaveform 1S1 at 7 V(see Note B)tPZHOutputWaveform 2S1 at Open(see Note B)1.5 V1.5 VtPLZ3.5 VVOL + 0.3 VVOLtPHZVOHVOH – 0.3 V0 VVOLTAGE WAVEFORMSENABLE AND DISABLE TIMESTESTtpdtPLZ/tPZLtPHZ/tPZHS1Open7 VOpenNOTES:A.CL includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.D.The outputs are measured one at a time with one transition per measurement.E.tPLZ and tPHZ are the same as tdis.F.tPZL and tPZH are the same as ten.G.tPLH and tPHL are the same as tpd.Figure 1. Load Circuit and Voltage Waveforms4POST OFFICE BOX 655303 DALLAS, TEXAS 75265•芯天下--http://oneic.com/PACKAGEOPTIONADDENDUM

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18-Sep-2008

PACKAGINGINFORMATION

OrderableDevice74CBT16245DGGRE474CBT16245DGGRG474CBT16245DGVRE474CBT16245DGVRG4SN74CBT16245DGGRSN74CBT16245DGVRSN74CBT16245DLSN74CBT16245DLG4SN74CBT16245DLRSN74CBT16245DLRG4

(1)

Status(1)ACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVE

PackageTypeTSSOPTSSOPTVSOPTVSOPTSSOPTVSOPSSOPSSOPSSOPSSOP

PackageDrawingDGGDGGDGVDGVDGGDGVDLDLDLDL

PinsPackageEcoPlan(2)

Qty48484848484848484848

2000Green(RoHS&

noSb/Br)2000Green(RoHS&

noSb/Br)2000Green(RoHS&

noSb/Br)2000Green(RoHS&

noSb/Br)2000Green(RoHS&

noSb/Br)2000Green(RoHS&

noSb/Br)2525

Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)

Lead/BallFinishCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAU

MSLPeakTemp(3)Level-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIM

1000Green(RoHS&

noSb/Br)1000Green(RoHS&

noSb/Br)

Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.

LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.

NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.

PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.

(2)

EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.

Pb-Free(RoHS):TI'sterms\"Lead-Free\"or\"Pb-Free\"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.

Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.

Green(RoHS&noSb/Br):TIdefines\"Green\"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)

(3)

MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.

ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.Effortsareunderwaytobetterintegrateinformationfromthirdparties.TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.

InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis.

Addendum-Page1

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PACKAGEOPTIONADDENDUM

www.ti.com

18-Sep-2008

OTHERQUALIFIEDVERSIONSOFSN74CBT16245:•Automotive:SN74CBT16245-Q1

NOTE:QualifiedVersionDefinitions:

•Automotive-Q100devicesqualifiedforhigh-reliabilityautomotiveapplicationstargetingzerodefects

Addendum-Page2

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PACKAGEMATERIALSINFORMATION

www.ti.com

11-Aug-2009

TAPEANDREELINFORMATION

*Alldimensionsarenominal

Device

PackagePackagePinsTypeDrawingTSSOPTVSOPSSOP

DGGDGVDL

484848

SPQ

ReelReelA0DiameterWidth(mm)(mm)W1(mm)330.0330.0330.0

24.416.432.4

8.67.111.35

B0(mm)15.810.216.2

K0(mm)1.81.63.1

P1(mm)12.012.016.0

WPin1(mm)Quadrant24.016.032.0

Q1Q1Q1

SN74CBT16245DGGRSN74CBT16245DGVRSN74CBT16245DLR

200020001000

PackMaterials-Page1

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PACKAGEMATERIALSINFORMATION

www.ti.com

11-Aug-2009

*Alldimensionsarenominal

Device

SN74CBT16245DGGRSN74CBT16245DGVRSN74CBT16245DLR

PackageType

TSSOPTVSOPSSOP

PackageDrawing

DGGDGVDL

Pins484848

SPQ200020001000

Length(mm)

346.0346.0346.0

Width(mm)346.0346.0346.0

Height(mm)

41.033.049.0

PackMaterials-Page2

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MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 MECHANICAL DATA DL (R-PDSO-G**) 48 PINS SHOWN0.025 (0,635)PLASTIC SMALL-OUTLINE PACKAGE0.0135 (0,343)0.008 (0,203)250.005 (0,13)M480.010 (0,25)0.005 (0,13)0.299 (7,59)0.291 (7,39)0.420 (10,67)0.395 (10,03)Gage Plane0.010 (0,25)1A240°–ā8°0.040 (1,02)0.020 (0,51)Seating Plane0.110 (2,79) MAX0.008 (0,20) MIN0.004 (0,10)PINS **DIMA MAX280.380(9,65)0.370(9,40)480.630(16,00)0.620(15,75)560.730(18,54)0.720(18,29)4040048/E 12/01A MINNOTES:A.B.C.D.All linear dimensions are in inches (millimeters).This drawing is subject to change without notice.Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).Falls within JEDEC MO-118POST OFFICE BOX 655303 DALLAS, TEXAS 75265•芯天下--http://oneic.com/MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 MECHANICAL DATA DGG (R-PDSO-G**) 48 PINS SHOWNPLASTIC SMALL-OUTLINE PACKAGE0,50480,270,17250,08M6,206,008,307,900,15 NOMGage Plane0,250°–8°A0,750,50124Seating Plane1,20 MAX0,150,05PINS **DIMA MAX0,1048566412,6014,1017,10A MIN12,4013,9016,904040078/F 12/97NOTES:A.B.C.D.All linear dimensions are in millimeters.This drawing is subject to change without notice.Body dimensions do not include mold protrusion not to exceed 0,15.Falls within JEDEC MO-153POST OFFICE BOX 655303 DALLAS, TEXAS 75265•芯天下--http://oneic.com/MECHANICAL DATAMPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000DGV (R-PDSO-G**) 24 PINS SHOWN0,230,1313PLASTIC SMALL-OUTLINE 0,40240,07M0,16 NOM4,504,306,606,20Gage Plane0,250°–ā8°1A120,750,50Seating Plane1,20 MAX0,150,050,08PINS **DIMA MAXA MIN143,703,50163,703,50205,104,90245,104,90387,907,70489,809,605611,4011,204073251/E 08/00NOTES:A.B.C.D.All linear dimensions are in millimeters.This drawing is subject to change without notice.Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.Falls within JEDEC:24/48 Pins – MO-15314/16/20/56 Pins – MO-194POST OFFICE BOX 655303 DALLAS, TEXAS 75265•芯天下--http://oneic.com/IMPORTANTNOTICE

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