TIBPAL 16L8-15C, TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8-15CTIBPAL 16L8-20M, TIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16R8-20MHIGH-PERFORMANCE IMPACT™ PAL® CIRCUITSSRPS019A – FEBRUARY 1984 – REVISED APRIL 2000DHigh-Performance Operation:DDDDPropagation DelayC Suffix...15 ns MaxM Suffix...20 ns MaxFunctionally Equivalent, but Faster ThanPAL16L8A, PAL16R4A, PAL16R6A, andPAL16R8APower-Up Clear on Registered Devices (AllRegister Outputs Are Set High, but VoltageLevels at the Output Pins Go Low)Package Options Include Both Plastic andCeramic Chip Carriers in Addition toPlastic and Ceramic DIPsDependable Texas Instruments Quality andReliabilityIINPUTS108883-STATEOOUTPUTS2000REGISTEREDQOUTPUTS04 (3-statebuffers)6 (3-statebuffers)8 (3-statebuffers)I/OPORTS6420TIBPAL16L8’C SUFFIX...J OR N PACKAGEM SUFFIX...J OR W PACKAGE(TOP VIEW)IIIIIIIIIGND1234567891020191817161514131211VCCOI/OI/OI/OI/OI/OI/OOIDEVICEPAL16L8PAL16R4PAL16R6PAL16R8TIBPAL16L8’C SUFFIX...FN PACKAGEM SUFFIX...FK PACKAGE(TOP VIEW)IIIVCC32descriptionThese programmable array logic devices featurehigh speed and functional equivalency whencompared with currently available devices. TheseIMPACT™ circuits combine the latest AdvancedLow-Power Schottky technology with proventitanium-tungsten fuses to provide reliable,high-performance substitutes for conventionalTTL logic. Their easy programmability allows forquick design of custom functions and typicallyresults in a more compact circuit board. Inaddition, chip carriers are available for furtherreduction in board space.The TIBPAL16’ C series is characterized from 0°Cto 75°C. The TIBPAL16’ M series is characterizedfor operation over the full military temperaturerange of –55°C to 125°C.IIIII456781201918171615OI/OI/OI/OI/OI/O14910111213Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.These devices are covered by U.S. Patent 4,410,987.IMPACT is a trademark of Texas Instruments.PAL is a registered trademark of Advanced Micro Devices Inc.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright © 2000, Texas Instruments IncorporatedPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•IGNDIOI/O1SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8-15CTIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16R8-20MHIGH-PERFORMANCE IMPACT™ PAL® CIRCUITSTIBPAL16R4’C SUFFIX...J OR N PACKAGEM SUFFIX...J OR W PACKAGE(TOP VIEW)TIBPAL16R4’C SUFFIX...FN PACKAGEM SUFFIX...FK PACKAGE(TOP VIEW) IICLKVCC321011TIBPAL16R6’C SUFFIX...J OR N PACKAGEM SUFFIX...J OR W PACKAGE(TOP VIEW)TIBPAL16R6’C SUFFIX...FN PACKAGEM SUFFIX...FK PACKAGE(TOP VIEW)IICLKVCCIGNDCLKIIIIIIIIGND123456789201918171615141312VCCI/OI/OQQQQI/OI/OOEIIIII456781201918171615I/OI/OQQQQI/O171615149101112131011TIBPAL16R8’C SUFFIX...J OR N PACKAGEM SUFFIX...J OR W PACKAGE(TOP VIEW)TIBPAL16R8’C SUFFIX...FN PACKAGEM SUFFIX...FK PACKAGE(TOP VIEW)10112POST OFFICE BOX 655303 DALLAS, TEXAS 75265•IGNDCLKIIIIIIIIGND123456789201918171615141312VCCQQQQQQQQOEIICLKVCCIGNDCLKIIIIIIIIGND123456789201918171615141312VCCI/OQQQQQQI/OOEIIIII45678321201918OEI/OI/OQQQQQ120191817161514910111213IIIII4567832QQQQQQ14910111213OEQQOEI/OQ TIBPAL 16L8-15C, TIBPAL 16R4-15CTIBPAL 16L8-20M, TIBPAL 16R4-20MHIGH-PERFORMANCE IMPACT™ PAL® CIRCUITSSRPS019A – FEBRUARY 1984 – REVISED APRIL 2000functional block diagrams (positive logic)TIBPAL16L8’&32 × 647716 ×7761677776EN≥1OOI/OI/OI/OI/OI/OI/OI1016TIBPAL16R4’OECLK&32 × 648881684416777744denotes fused inputsEN≥1I/OI/OI/OI/OQ≥1EN 2C1I = 121DQQQI816 ×POST OFFICE BOX 655303 DALLAS, TEXAS 75265•3SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000TIBPAL 16R6-15C, TIBPAL 16R8-15CTIBPAL 16R6-20M, TIBPAL 16R8-20MHIGH-PERFORMANCE IMPACT™ PAL® CIRCUITSfunctional block diagrams (positive logic)TIBPAL16R6’OECLK&32 × 64888168682168EN≥1QQQ≥1EN 2C1I = 121DQQQ I816 ×7726I/OI/OTIBPAL16R8’OECLK&32 × 6488816888168888denotes fused inputsQQQQQ≥1EN 2C1I = 121DQQQI816 ×4POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TIBPAL 16L8-15CTIBPAL 16L8-20MHIGH-PERFORMANCE IMPACT™ PAL® CIRCUITSSRPS019A – FEBRUARY 1984 – REVISED APRIL 2000logic diagram (positive logic)I1Increment048121620242831FirstFuseNumbers03264961281601922242562883203523844164484805125445766086406727047367688008328648969289609921024105610881120115211841216124812801312134413761408144014721504153615681600163216641696172817601792182418561888192019521984201619OI218I/OI317I/OI416I/OI515I/OI614I/OI713I/OI812OI911IFuse number = First fuse number + IncrementPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•5SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000TIBPAL 16R4-15CTIBPAL 16R4-20MHIGH-PERFORMANCE IMPACT™ PAL® CIRCUITSlogic diagram (positive logic)CLK1Increment048121620242831FirstFuseNumbers032649612816019222425628832035238441644848051254457660864067270473676880083286489692896099210241056108811201152118412161248128013121344137614081440147215041536156816001632166416961728176017921824185618881920195219842016 19I/OI218I/OI3I = 11DC117QI4I = 11DC116QI5I = 11DC115QI6I = 11DC114QI713I/OI812I/OI911Fuse number = First fuse number + IncrementOE6POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TIBPAL 16R6-15CTIBPAL 16R6-20MHIGH-PERFORMANCE IMPACT™ PAL® CIRCUITSSRPS019A – FEBRUARY 1984 – REVISED APRIL 2000logic diagram (positive logic)CLK1Increment048121620242831FirstFuseNumbers03264961281601922242562883203523844164484805125445766086406727047367688008328648969289609921024105610881120115211841216124812801312134413761408144014721504153615681600163216641696172817601792182418561888192019521984201619I/OI2I = 11DC118QI3I = 11DC117QI4I = 11DC116QI5I = 11DC115QI6I = 11DC114QI7I = 11DC113QI812I/OI911OEFuse number = First fuse number + IncrementPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•7SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000TIBPAL 16R8-15CTIBPAL 16R8-20MHIGH-PERFORMANCE IMPACT™ PAL® CIRCUITSlogic diagram (positive logic)CLK1Increment048121620242831FirstFuseNumbers032649612816019222425628832035238441644848051254457660864067270473676880083286489692896099210241056108811201152118412161248128013121344137614081440147215041536156816001632166416961728176017921824185618881920195219842016 I = 11DC119QI2I = 11DC118QI3I = 11DC117QI4I = 11DC116QI5I = 11DC115QI6I = 11DC114QI7I = 11DC113QI8I = 11DC112QI911OEFuse number = First fuse number + Increment8POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TIBPAL 16L8-15C, TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8-15CHIGH-PERFORMANCE IMPACT™ PAL® CIRCUITS SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000absolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VInput voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 VVoltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 VOperating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°CStorage temperature range, Tstg –65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°CNOTE 1:These ratings apply, except for programming pins, during a programming cycle.recommended operating conditionsMINVCCVIHVILIOHIOLfclocktwtsuthSupply voltageHigh-level input voltageLow-level input voltageHigh-level output currentLow-level output currentClock frequencyPulsedurationclock(seeNote2)Pulse duration, clock (see Note 2)Setup time, input or feedback before clock↑Hold time, input or feedback after clock↑HighLow0891504.752NOM5MAX5.255.50.8–3.22450UNITVVVmAmAMHznsnsnsTAOperating free-air temperature02575°CNOTE 2:The total clock period of clock high and clock low must not exceed clock frequency, fclock. The minimum pulse durations specified are forclock high or low only, but not for both simultaneously.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•9SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000TIBPAL 16L8-15C, TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8-15CHIGH-PERFORMANCE IMPACT™ PAL® CIRCUITS electrical characteristics over recommended operating free-air temperature rangePARAMETERVIKVOHVOLIOZHIOZLIIIIHIILIO‡ICCOutputsI/O portsOutputsI/O portsVCC = 4.75 V,VCC = 4.75 V,VCC = 4.75 V,VCC = 5.25 V,=525VVCC = 5.25 V,=525VVCC = 5.25 V,VCC = 5.25 V,VCC = 5.25 V,VCC = 5.25 V,VCC = 5.25 V,TEST CONDITIONSII = –18 mAIOH = –3.2 mAIOL = 24 mAVO = 2.7 V=27VVO = 0.4 V=04VVI = 5.5 VVI = 2.7 VVI = 0.4 VVO = 2.25 VVI = 0,Outputs open–30140MIN2.4TYP†3.30.350.520100–20–2500.120–0.2–125180MAX–1.5UNITVVVµAµAmAµAmAmAmA †All typical values are at VCC = 5 V, TA = 25°C.‡The output conditions have been chosen to produce a current that closely approximates one-half of the short-circuit output current, IOS.switching characteristics over recommended ranges of supply voltage and operating free-airtemperature (unless otherwise noted)PARAMETERfmaxtpdtpdtentdistentdisFROM(INPUT)I, I/OCLK↑OE↓OE↑I, I/OI, I/OTO(OUTPUT)O, I/OQQQO, I/OO, I/OR1 = 500 R1 500 Ω,R2 = 500 Ω,SFiSee Figure 3TEST CONDITIONSMIN50108871010151212101515TYP†MAXUNITMHznsnsnsnsnsns†All typical values are at VCC = 5 V, TA = 25°C.10POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TIBPAL 16L8-20M, TIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16R8-20MHIGH-PERFORMANCE IMPACT™ PAL® CIRCUITS SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000absolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VInput voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 VVoltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 VOperating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°CStorage temperature range, Tstg –65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°CNOTE 1:These ratings apply, except for programming pins, during a programming cycle.recommended operating conditionsMINVCCVIHVILIOHIOLfclocktwtsuthSupply voltageHigh-level input voltageLow-level input voltageHigh-level output currentLow-level output currentClock frequencyPulsedurationclock(seeNote2)Pulse duration, clock (see Note 2)Setup time, input or feedback before clock↑Hold time, input or feedback after clock↑HighLow010112004.52NOM5MAX5.55.50.8–21241.6UNITVVVmAmAMHznsnsnsTAOperating free-air temperature–5525125°CNOTE 2:The total clock period of clock high and clock low must not exceed clock frequency, fclock. The minimum pulse durations specified are forclock high or low only, but not for both simultaneously.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•11SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000TIBPAL 16L8-20M, TIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16R8-20MHIGH-PERFORMANCE IMPACT™ PAL® CIRCUITS electrical characteristics over recommended operating free-air temperature rangePARAMETERVIKVOHVOLIOZHIOZLIIOutputsI/O portsOutputsI/O portsPin 1, 11All othersPin 1, 11IIHI/O portsAll othersIILIOS‡ICCI/O portsAll othersVCC = 5.5 V,=55VVCC = 5.5 V,VCC = 5.5 V,VI = 0.4 V=04VVO = 0.5 VVI = 0,–30Outputs open140VCC = 5.5 V,VI = 2.7 VVCC = 4.5 V,VCC = 4.5 V,VCC = 4.5 V,VCC = 5.5 V,=55VVCC = 5.5 V,=55VVCC = 5.5 V,=55VTEST CONDITIONSII = –18 mAIOH = –2 mAIOL = 12 mAVO = 2.7 V=27VVO = 0.4 V=04VVI = 5.5 V=55VMIN2.4TYP†3.20.250.420100–20–2500.20.15010020–0.25–0.2–250190mAmAmAµAMAX–1.5UNITVVVµAµAmA †All typical values are at VCC = 5 V, TA = 25°C.‡Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set VO at 0.5 V to avoidtest-equipment degradation.switching characteristics over recommended ranges of supply voltage and operating free-airtemperature (unless otherwise noted)PARAMETERfmaxtpdtpdtentdistentdisFROM(INPUT)I, I/OCLK↑OE↓OE↑I, I/OI, I/OTO(OUTPUT)O, I/OQQQO, I/OO, I/OR1 390 Ω,R1 = 390 R2 = 750 Ω,SFiSee Figure 4TEST CONDITIONSMIN41.6108871010201515152020TYP†MAXUNITMHznsnsnsnsnsns†All typical values are at VCC = 5 V, TA = 25°C.12POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TIBPAL 16L8-15C, TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8-15CTIBPAL 16L8-20M, TIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16R8-20MHIGH-PERFORMANCE IMPACT™ PAL® CIRCUITSSRPS019A – FEBRUARY 1984 – REVISED APRIL 2000programming informationTexas Instruments programmable logic devices can be programmed using widely available software andinexpensive device programmers.Complete programming specifications, algorithms, and the latest information on hardware, software, andfirmware are available upon request. Information on programmers capable of programming Texas Instrumentsprogrammable logic also is available, upon request, from the nearest TI field sales office or local authorized TIdistributor, by calling Texas Instruments at +1 (972) 644–5580, or by visiting the TI Semiconductor Home Pageat www.ti.com/sc.preload procedure for registered outputs (see Figure 1 and Note 3)The output registers can be preloaded to any desired state during device testing. This permits any state to betested without having to step through the entire state-machine sequence. Each register is preloaded individuallyby following the steps given below.Step 1.Step 2.Step 3.Step 4.With VCC at 5 V and Pin 1 at VIL, raise Pin 11 to VIHH.Apply either VIL or VIH to the output corresponding to the register to be preloaded.Pulse Pin 1, clocking in preload data.Remove output voltage, then lower Pin 11 to VIL. Preload can be verified by observing thevoltage level at the output pin.Pin 11tdPin 1tsutwtdVIHHVILVIHVILVIHVILNOTE 3:td = tsu = th = 100 ns to 1000 ns VIHH = 10.25 V to 10.75 VVOHVOLRegistered I/OInputOutputFigure 1. Preload WaveformsPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•13SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000TIBPAL 16L8-15C, TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8-15CTIBPAL 16L8-20M, TIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16R8-20MHIGH-PERFORMANCE IMPACT™ PAL® CIRCUITSpower-up reset (see Figure 2) Following power up, all registers are set high. This feature provides extra flexibility to the system designer andis especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is importantthat the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not occur untilall applicable input and feedback setup times are met.VCC4 Vtpd†(600 ns TYP, 1000 ns MAX)Active-LowRegistered OutputVOH1.5 VVOLtsu‡CLKVIH1.5 Vtw†This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.‡This is the setup time for input or feedback.1.5 VVIL5 VFigure 2. Power-Up Reset Waveforms14POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TIBPAL 16L8-15C, TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8-15CHIGH-PERFORMANCE IMPACT™ PAL® CIRCUITS SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000PARAMETER MEASUREMENT INFORMATION7 VS1R1From OutputUnder TestCL(see Note A)R2TestPointLOAD CIRCUIT FOR 3-STATE OUTPUTSTimingInputtsuDataInput1.3 V3.5 V1.3 V0.3 Vth3.5 V1.3 V0.3 VVOLTAGE WAVEFORMSSETUP AND HOLD TIMESHigh-LevelPulse3.5 V1.3 Vtw1.3 V0.3 VLow-LevelPulse3.5 V1.3 V1.3 V0.3 VVOLTAGE WAVEFORMSPULSE DURATIONS3.5 VInputtpdIn-PhaseOutputtpdOut-of-PhaseOutput(see Note D)1.3 V1.3 V1.3 V1.3 V0.3 Vtpd1.3 Vtpd1.3 VVOHVOLOutputControl(low-levelenabling)tenWaveform 1S1 Closed(see Note B)ten3.5 V1.3 V1.3 V0.3 Vtdis≈3.5 VVOL + 0.3 VVOLtdisVOH1.3 VVOH – 0.3 V≈0 V1.3 VVOHVOLWaveform 2S1 Open(see Note B)VOLTAGE WAVEFORMSPROPAGATION DELAY TIMESVOLTAGE WAVEFORMSENABLE AND DISABLE TIMES, 3-STATE OUTPUTSNOTES:A.CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.B.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control.C.All input pulses have the following characteristics:PRR ≤1 MHz, tr = tf ≤ 2 ns, duty cycle = 50%D.When measuring propagation delay times of 3-state outputs from low to high, switch S1 is closed.When measuring propagation delay times of 3-state outputs from high to low, switch S1 is open.E.Equivalent loads may be used for testing.Figure 3. Load Circuit and Voltage WaveformsPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•15SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000TIBPAL 16L8-20M, TIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16R8-20MHIGH-PERFORMANCE IMPACT™ PAL® CIRCUITS PARAMETER MEASUREMENT INFORMATION5 V S1R1From OutputUnder TestCL(see Note A)R2TestPointLOAD CIRCUIT FOR 3-STATE OUTPUTSTimingInputtsuDataInput1.5 V3 V1.5 V0th3 V1.5 V0VOLTAGE WAVEFORMSSETUP AND HOLD TIMESHigh-LevelPulse3 V1.5 Vtw1.5 V0Low-LevelPulse3 V1.5 V1.5 V0VOLTAGE WAVEFORMSPULSE DURATIONS3 VInputtpdIn-PhaseOutputtpdOut-of-PhaseOutput(see Note D)1.5 V1.5 V1.5 V1.5 V0tpd1.5 Vtpd1.5 VVOLVOHVOLOutputControl(low-levelenabling)tenWaveform 1S1 Closed(see Note B)ten3 V1.5 V1.5 V0tdis1.5 VtdisVOH1.5 VVOH – 0.5 V≈0 V≈3.3 VVOL + 0.5 VVOLVOHWaveform 2S1 Open(see Note B)VOLTAGE WAVEFORMSPROPAGATION DELAY TIMESVOLTAGE WAVEFORMSENABLE AND DISABLE TIMES, 3-STATE OUTPUTSNOTES:A.CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.B.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control.C.All input pulses have the following characteristics:PRR ≤10 MHz, tr = tf ≤ 2 ns, duty cycle = 50%D.When measuring propagation delay times of 3-state outputs, switch S1 is closed.E.Equivalent loads may be used for testing.Figure 4. Load Circuit and Voltage Waveforms16POST OFFICE BOX 655303 DALLAS, TEXAS 75265•PACKAGEOPTIONADDENDUM
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PACKAGINGINFORMATION
OrderableDevice5962-85155012A5962-8515501RA5962-8515501SA5962-85155022A5962-8515502RA5962-8515502SA5962-85155032A5962-8515503RA5962-8515503SA5962-85155042A5962-8515504RA5962-8515504SAJM38510/50601BRAJM38510/50602BRAJM38510/50603BRAJM38510/50604BRATIBPAL16L8-15CFNTIBPAL16L8-15CNTIBPAL16L8-20MFKBTIBPAL16L8-20MJTIBPAL16L8-20MJBTIBPAL16L8-20MWBTIBPAL16R4-15CFNTIBPAL16R4-15CJTIBPAL16R4-15CNTIBPAL16R4-20MFKBTIBPAL16R4-20MJTIBPAL16R4-20MJBTIBPAL16R4-20MWBTIBPAL16R6-15CFNTIBPAL16R6-15CNTIBPAL16R6-20MFKBTIBPAL16R6-20MJBTIBPAL16R6-20MWBTIBPAL16R8-15CFNTIBPAL16R8-15CNTIBPAL16R8-20MFKBTIBPAL16R8-20MJTIBPAL16R8-20MJB
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PackageTypeLCCCCDIPCFPLCCCCDIPCFPLCCCCDIPCFPLCCCCDIPCFPCDIPCDIPCDIPCDIPPLCCPDIPLCCCCDIPCDIPCFPPLCCCDIPPDIPLCCCCDIPCDIPCFPPLCCPDIPLCCCCDIPCFPPLCCPDIPLCCCCDIPCDIP
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TBDTBDTBDTBDTBDTBDTBDTBDTBDTBDTBDTBDTBDTBDTBDTBDTBDPb-Free(RoHS)TBDTBDTBDTBDTBDTBDPb-Free(RoHS)TBDTBDTBDTBDTBDPb-Free(RoHS)TBDTBDTBDTBDPb-Free(RoHS)TBDTBDTBD
Lead/BallFinish
MSLPeakTemp(3)
POST-PLATEN/AforPkgType
A42CallTIA42CallTIA42CallTIA42CallTIA42A42A42A42CUSNPBCUNIPDAU
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POST-PLATEN/AforPkgType
POST-PLATEN/AforPkgType
POST-PLATEN/AforPkgType
POST-PLATEN/AforPkgType
A42A42CallTICUSNPBCallTICUNIPDAU
N/AforPkgTypeN/AforPkgTypeN/AforPkgTypeLevel-1-220C-UNLIMCallTI
N/AforPkgType
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A42A42CallTICUSNPBCUNIPDAU
N/AforPkgTypeN/AforPkgTypeN/AforPkgTypeLevel-1-220C-UNLIMN/AforPkgType
POST-PLATEN/AforPkgType
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POST-PLATEN/AforPkgType
A42A42
N/AforPkgTypeN/AforPkgType
Addendum-Page1
PACKAGEOPTIONADDENDUM
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OrderableDeviceTIBPAL16R8-20MWB
(1)
Status(1)ACTIVE
PackageTypeCFP
PackageDrawing
W
PinsPackageEcoPlan(2)
Qty20
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TBD
Lead/BallFinish
CallTI
MSLPeakTemp(3)N/AforPkgType
Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)
EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms\"Lead-Free\"or\"Pb-Free\"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.
Green(RoHS&noSb/Br):TIdefines\"Green\"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)
(3)
MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.Effortsareunderwaytobetterintegrateinformationfromthirdparties.TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.
InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis.
Addendum-Page2
MECHANICAL DATA MLCC006B – OCTOBER 1996FK (S-CQCC-N**) 28 TERMINAL SHOWNLEADLESS CERAMIC CHIP CARRIER18171615141312NO. OFTERMINALS**111028987668584445220AMIN0.342(8,69)0.442(11,23)0.640(16,26)0.739(18,78)0.938(23,83)1.141(28,99)MAX0.358(9,09)0.458(11,63)0.660(16,76)0.761(19,32)0.962(24,43)1.165(29,59)MIN0.307(7,80)0.406(10,31)0.495(12,58)0.495(12,58)0.850(21,6)1.047(26,6)BMAX0.358(9,09)0.458(11,63)0.560(14,22)0.560(14,22)0.858(21,8)1.063(27,0)192021B SQ22A SQ23242526272812340.080 (2,03)0.064 (1,63)0.020 (0,51)0.010 (0,25)0.020 (0,51)0.010 (0,25)0.055 (1,40)0.045 (1,14)0.045 (1,14)0.035 (0,89)0.028 (0,71)0.022 (0,54)0.050 (1,27)0.045 (1,14)0.035 (0,89)4040140/D 10/96NOTES:A.B.C.D.E.All linear dimensions are in inches (millimeters).This drawing is subject to change without notice.This package can be hermetically sealed with a metal lid.The terminals are gold plated.Falls within JEDEC MS-004POST OFFICE BOX 655303 DALLAS, TEXAS 75265• MECHANICAL DATA MPLC004A – OCTOBER 1994FN (S-PQCC-J**) 20 PIN SHOWNPLASTIC J-LEADED CHIP CARRIERSeating Plane0.004 (0,10)DD131190.032 (0,81)0.026 (0,66)418D2/E20.180 (4,57) MAX0.120 (3,05)0.090 (2,29)0.020 (0,51) MINEE1D2/E28149130.050 (1,27)0.008 (0,20) NOM0.021 (0,53)0.013 (0,33)0.007 (0,18)MNO. OFPINS**202844526884D/EMIN0.385 (9,78)0.485 (12,32)0.685 (17,40)0.785 (19,94)0.985 (25,02)1.185 (30,10)MAX0.395 (10,03)0.495 (12,57)0.695 (17,65)0.795 (20,19)0.995 (25,27)1.195 (30,35)MIND1/E1MAX0.356 (9,04)0.456 (11,58)0.656 (16,66)0.756 (19,20)0.958 (24,33)1.158 (29,41)MIND2/E2MAX0.169 (4,29)0.219 (5,56)0.319 (8,10)0.369 (9,37)0.469 (11,91)0.569 (14,45)4040005/B 03/950.350 (8,89)0.450 (11,43)0.650 (16,51)0.750 (19,05)0.950 (24,13)1.150 (29,21)0.141 (3,58)0.191 (4,85)0.291 (7,39)0.341 (8,66)0.441 (11,20)0.541 (13,74)NOTES:A.All linear dimensions are in inches (millimeters).B.This drawing is subject to change without notice.C.Falls within JEDEC MS-018POST OFFICE BOX 655303 DALLAS, TEXAS 75265•1IMPORTANTNOTICE
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