专利名称：PERFORMING MULTI-CONVOLUTION
OPERATIONS IN A PARALLEL PROCESSINGSYSTEM
发明人：Sharanyan CHETLUR,Bryan CATANZARO申请号：US14838291申请日：20150827
公开号：US20160062947A1公开日：20160303
专利附图：
摘要：In one embodiment of the present invention a convolution engine configures aparallel processing pipeline to perform multi-convolution operations. More specifically,
the convolution engine configures the parallel processing pipeline to independentlygenerate and process individual image tiles. In operation, for each image tile, the pipelinecalculates source locations included in an input image batch. Notably, the source
locations reflect the contribution of the image tile to an output tile of an output matrix—the result of the multi-convolution operation. Subsequently, the pipeline copies datafrom the source locations to the image tile. Similarly, the pipeline copies data from afilter stack to a filter tile. The pipeline then performs matrix multiplication operationsbetween the image tile and the filter tile to generate data included in the correspondingoutput tile. To optimize both on-chip memory usage and execution time, the pipelinecreates each image tile in on-chip memory as-needed.
申请人：NVIDIA CORPORATION
地址：Santa Clara CA US
国籍：US
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