LTC2240-1010-Bit, 170Msps ADCFEATURES
Sample Rate: 170Mspsn 60.6dB SNRn 80dB SFDRn 1.2GHz Full Power Bandwidth S/Hn Single 2.5V Supplyn Low Power Dissipation: 445mWn LVDS, CMOS, or Demultiplexed CMOS Outputsn Selectable Input Ranges: ±0.5V or ±1Vn No Missing Codesn Optional Clock Duty Cycle Stabilizern Shutdown and Nap Modesn Data Ready Output Clockn Pin Compatible Family 250Msps: LTC2242-12 (12-Bit), LTC2242-10 (10-Bit) 210Msps: LTC2241-12 (12-Bit), LTC2241-10 (10-Bit) 170Msps: LTC2240-12 (12-Bit), LTC2240-10 (10-Bit) 185Msps: LTC2220-1 (12-Bit)* 170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)* 135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)*n 64-Pin 9mm × 9mm QFN PackagenDESCRIPTION
The LTC®2240-10 is a 170Msps, sampling 10-bit A/D con-verter designed for digitizing high frequency, wide dynamic range signals. The LTC2240-10 is perfect for demanding communications applications with AC performance that includes 60.6dB SNR and 80dB SFDR. Ultralow jitter of 95fsRMS allows IF undersampling with excellent noise performance.DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ) and no missing codes over temperature.The digital outputs can be either differential LVDS, or single-ended CMOS. There are three format options for the CMOS outputs: a single bus running at the full data rate or two demultiplexed buses running at half data rate with either interleaved or simultaneous update. A separate output power supply allows the CMOS output swing to range from 0.5V to 2.625V.The ENC+ and ENC– inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance over a wide range of clock duty cycles.L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. *LTC2220-1, LTC2220, LTC2221, LTC2230, LTC2231 are 3.3V parts.APPLICATIONS
n n n nWireless and Wired Broadband CommunicationCable Head-End SystemsPower Amplifi er LinearizationCommunications Test EquipmentTYPICAL APPLICATION
2.5VVDDREFHREFL
FLEXIBLEREFERENCE0.5VTO 2.625VOVDDD9•••D0SNR (dBFS)626160595857
OGNDCLOCK/DUTYCYCLECONTROL224010 TA01224010 G10
SNR vs Input Frequency2V RANGE+ANALOGINPUT–INPUTS/H10-BITPIPELINEDADC CORECORRECTIONLOGICOUTPUTDRIVERSCMOSORLVDS1V RANGE5655
01002003004005006007008009001000
INPUT FREQUENCY (MHz)
ENCODEINPUT
224010fb1
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LTC2240-10ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDD) ...............................................2.8VDigital Output Ground Voltage (OGND) ........–0.3V to 1VAnalog Input Voltage (Note 3) .......–0.3V to (VDD + 0.3V)Digital Input Voltage ......................–0.3V to (VDD + 0.3V)Digital Output Voltage ................–0.3V to (OVDD + 0.3V)OVDD = VDD (Notes 1, 2)Power Dissipation .............................................1500mWOperating Temperature Range LTC2240C-10 ...........................................0°C to 70°C LTC2240I-10 ........................................–40°C to 85°CStorage Temperature Range ...................–65°C to 150°CPIN CONFIGURATION
TOP VIEW
64 GND63 VDD62 VDD61 GND60 VCM59 SENSE58 MODE57 LVDS56 OF+/OFA55 OF–/DA954 D9+/DA853 D9–/DA752 D8+/DA651 D8–/DA550 OGND49 OVDDAIN+1AIN+ 2AIN– 3AIN– 4REFHA 5REFHA 6REFLB7REFLB8REFHB 9REFHB 10REFLA 11REFLA 12VDD 13VDD 14VDD 15GND 16
65
48 D7+/DA447 D7–/DA346 D6+/DA245 D6–/DA144 D5+/DA043 D5–/DNC42 OVDD41 OGND40 D4+/DNC
39 D4–/CLKOUTA38 D3+/CLKOUTB37 D3–/OFB
36 CLKOUT+/DB935 CLKOUT–/DB834 OVDD33 OGND
UP PACKAGE
64-LEAD (9mm × 9mm) PLASTIC QFN
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
TJMAX = 150°C,θJA = 20°C/W
ORDER INFORMATION
LEAD FREE FINISHLTC2240CUP-10#PBFLTC2240IUP-10#PBFLEAD BASED FINISHLTC2240CUP-10LTC2240IUP-10TAPE AND REELLTC2240CUP-10#TRPBFLTC2240IUP-10#TRPBFTAPE AND REELLTC2240CUP-10#TRLTC2240IUP-10#TRPART MARKING*LTC2240UP-10LTC2240UP-10PART MARKING*LTC2240UP-10LTC2240UP-10PACKAGE DESCRIPTION64-Lead (9mm × 9mm) Plastic QFN64-Lead (9mm × 9mm) Plastic QFNPACKAGE DESCRIPTION64-Lead (9mm × 9mm) Plastic QFN64-Lead (9mm × 9mm) Plastic QFNTEMPERATURE RANGE0°C to 70°C–40°C to 85°CTEMPERATURE RANGE0°C to 70°C–40°C to 85°CConsult LTC Marketing for parts specifi ed with wider operating temperature ranges. *Temperature grades are identifi ed by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/ENC+17ENC– 18SHDN19OE20DNC 21DNC 22DNC/DB0 23DNC/DB1 24OGND 25OVDD 26D0–/DB2 27D0+/DB3 28D1–/DB4 29D1+/DB5 30D2–/DB6 31D2+/DB7 32224010fb2
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LTC2240-10CONVERTER CHARACTERISTICS
PARAMETERResolution (No Missing Codes)Integral Linearity ErrorDifferential Linearity ErrorOffset ErrorGain ErrorOffset DriftFull-Scale DriftTransition NoiseInternal ReferenceExternal ReferenceSENSE = 1VDifferential Analog Input (Note 5)Differential Analog Input(Note 6)External ReferenceThe l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)CONDITIONSlllllMIN10–0.8–0.6–15–3.8TYP±0.3±0.1±5±0.7±10±60±450.18MAX0.80.6153.8UNITSBitsLSBLSBmV%FSμV/Cppm/Cppm/CLSBRMSANALOG INPUTThe l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)SYMBOLVINVIN, CMIINISENSEIMODEILVDStAPtJITTERPARAMETERAnalog Input Range (AIN+ – AIN–)Analog Input Common Mode (AIN+ + AIN–)/2Analog Input Leakage CurrentSENSE Input LeakageMODE Pin Pull-Down Current to GNDLVDS Pin Pull-Down Current to GNDSample and Hold Acquisition Delay TimeSample and Hold Acquisition Delay Time JitterFull Power BandwidthFigure 8 Test CircuitCONDITIONS2.375V < VDD < 2.625V (Note 7)Differential Input (Note 7)0 < AIN+, AIN– < VDD0V < SENSE < 1VllllMIN1.2–1–1TYP±0.5 to ±11.25MAX1.311UNITSVVμAμAμAμAnsfsRMSMHz770.4951200DYNAMIC ACCURACY
SYMBOLSNRPARAMETERThe l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. AIN = –1dBFS. (Note 4)CONDITIONS10MHz Input70MHz Input140MHz Input240MHz InputSFDRSpurious Free Dynamic Range2nd or 3rd Harmonic(Note 11)10MHz Input70MHz Input140MHz Input240MHz InputSpurious Free Dynamic Range4th Harmonic or Higher(Note 11)10MHz Input70MHz Input140MHz Input240MHz InputlllMIN59.7TYP60.660.660.560.580MAXUNITSdBdBdBdBdBdBdBdBdBdBdBdBSignal-to-Noise Ratio (Note 10)657574728574858585224010fb3
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LTC2240-10DYNAMIC ACCURACY
SYMBOLS/(N+D)PARAMETERSignal-to-Noise PlusDistortion Ratio(Note 12)The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. AIN = –1dBFS. (Note 4)CONDITIONS10MHz Input70MHz Input140MHz Input240MHz InputIMDIntermodulation DistortionfIN1 = 135MHz, fIN2 = 140MHzlMIN59.1TYP60.560.560.460.181MAXUNITSdBdBdBdBdBcINTERNAL REFERENCE CHARACTERISTICS(Note 4)PARAMETERVCM Output VoltageVCM Output TempcoVCM Line RegulationVCM Output Resistance2.375V < VDD < 2.625V–1mA < IOUT < 1mACONDITIONSIOUT = 0MIN1.225TYP1.25±3532MAX1.275UNITSVppm/°CmV/VΩDIGITAL INPUTS AND DIGITAL OUTPUTS
SYMBOLVIDVICMRINCINVIHVILIINCINOVDD = 2.5VCOZISOURCEISINKVOHVOLOVDD = 1.8VVOHVOLHigh Level Output VoltageLow Level Output VoltageIO = –500μAIO = 500μAHi-Z Output CapacitanceOutput Source CurrentOutput Sink CurrentHigh Level Output VoltageLow Level Output VoltageOE = High (Note 7)VOUT = 0VVOUT = 2.5VIO = –10μAIO = –500μAPARAMETERDifferential Input VoltageCommon Mode Input VoltageInput ResistanceInput CapacitanceHigh Level Input VoltageLow Level Input VoltageInput CurrentInput Capacitance(Note 7)VDD = 2.5VVDD = 2.5VVIN = 0V to VDD(Note 7)CONDITIONS(Note 7)Internally SetExternally Set (Note 7)ENCODE INPUTS (ENC+, ENC–)The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)MINllTYPMAXUNITSV0.21.21.51.54.822.0VVkΩpFVLOGIC INPUTS (OE, SHDN)lll1.70.7–10310VμApFLOGIC OUTPUTS (CMOS MODE)337232.4952.450.0050.071.750.07pFmAmAVVVVVV224010fb4
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LTC2240-10DIGITAL INPUTS AND DIGITAL OUTPUTS
SYMBOLVODVOSPARAMETERDifferential Output VoltageOutput Common Mode VoltageCONDITIONS100Ω Differential Load100Ω Differential LoadllThe l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)MIN2471.125TYP3501.250MAX4541.375UNITSmVVLOGIC OUTPUTS (LVDS MODE)POWER REQUIREMENTS
SYMBOLV DDPSLEEPPNAPLVDS OUTPUT MODOVDDIVDDIOVDDPDISSOVDDIVDDPDISSOutput Supply VoltagAnalog Supply CurrentOutput Supply CurrentPower DissipationOutput Supply VoltageAnalog Supply CurrentPower DissipationPARAMETERAnalog Supply VoltageSleep Mode PowerNap Mode PowerThe l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 9)CONDITIONS(Note 8)SHDN = High, OE = High, No CLKSHDN = High, OE = Low, No CLK(Note 8)lllllMIN2.375TYP2.5128MAX2.625UNITSVmWmW2.3752.5170585702.625185706382.625185VmAmAmWVmAmWCMOS OUTPUT MODE(Note 8)(Note 7)ll0.52.5170445TIMING CHARACTERISTICS
SYMBOLfStLtHtAPtOELVDS OUTPUT MODEtDtCENC to DATA DelayENC to CLKOUT DelayDATA to CLKOUT SkewRise TimeFall TimePipeline LatencyCMOS OUTPUT MODEtDtCENC to DATA DelayENC to CLKOUT DelayPARAMETERSampling FrequencyENC Low Time (Note 7)ENC High Time (Note 7)Sample-and-Hold Aperture DelayOutput Enable DelayThe l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)CONDITIONS(Note 8)Duty Cycle Stabilizer OffDuty Cycle Stabilizer OnDuty Cycle Stabilizer OffDuty Cycle Stabilizer On(Note 7)(Note 7)(Note 7)(tC – tD) (Note 7)llllllMIN12.791.52.791.5TYP2.942.942.942.940.45MAX170500500500500102.82.80.6UNITSMHznsnsnsnsnsnsnsnsnsnsnsCycleslll11–0.61.71.700.50.55(Note 7)(Note 7)ll111.71.72.82.8nsns224010fb5
LTC2240-10TIMING CHARACTERISTICS
SYMBOLPipeline LatencyPARAMETERDATA to CLKOUT SkewFull Rate CMOSDemuxed InterleavedDemuxed SimultaneousThe l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)CONDITIONS(tC – tD) (Note 7)lMIN–0.6TYP0555 and 6MAX0.6UNITSnsCyclesCyclesCyclesELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted).Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup.Note 4: VDD = 2.5V, fSAMPLE = 170MHz, LVDS outputs, differential ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted.Note 5: Integral nonlinearity is defi ned as the deviation of a code from a “best straight line” fi t to the transfer curve. The deviation is measured from the center of the quantization band.Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code fl ickers between 00 0000 0000 and 11 1111 1111 in 2’s complement output mode.Note 7: Guaranteed by design, not subject to test.Note 8: Recommended operating conditions.Note 9: VDD = 2.5V, fSAMPLE = 170MHz, differential ENC+/ENC– = 2VP-P sine wave, input range = 1VP-P with differential drive, output CLOAD = 5pF.Note 10: SNR minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.2dB lower.Note 11: SFDR minimum values are for LVDS mode. Typical values are for both LVDS and CMOS modes.Note 12: SINAD minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.2dB lower.TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity1.00.80.60.4INL (LSB)0.20–0.2–0.4–0.6–0.8–1.0
0
256
512
OUTPUT CODE
768
1024
224010 G01
(TA = 25°C unless otherwise noted, Note 4)Differential Nonlinearity8192 Point FFT, fIN = 5MHz, –1dB, 2V Range, LVDS Mode224010fb6
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LTC2240-10TYPICAL PERFORMANCE CHARACTERISTICS
8192 Point FFT, fIN = 70MHz, –1dB, 2V Range, LVDS Mode0–10–20–30AMPLITUDE (dB)AMPLITUDE (dB)–40–50–60–70–80–90–100–110
0
10
20
30405060FREQUENCY (MHz)
70
80
(TA = 25°C unless otherwise noted, Note 4)8192 Point FFT, fIN = 240MHz, –1dB, 2V Range, LVDS Mode0–10–20–30–40–50–60–70–80–90–100–110
0
10
20
30405060FREQUENCY (MHz)
70
80
8192 Point FFT, fIN = 140MHz, –1dB, 2V Range, LVDS Mode224010 G04224010 G06
8192 Point FFT, fIN = 500MHz, –1dB, 1V Range, LVDS Mode8192 Point FFT, fIN = 1GHz, –1dB, 1V Range, LVDS Mode8192 Point 2-Tone FFT, fIN = 135MHz and 140MHz, –1dB, 2V Range, LVDS ModeSNR vs Input Frequency, –1dB, LVDS Mode8580
2V RANGE75SFDR (dBFS)SFDR (HD2 and HD3) vs Input Frequency, –1dB, LVDS Mode9590
SFDR (HD4+) vs Input Frequency, –1dB, LVDS Mode2V RANGE85SFDR (dBFS)1V RANGE8075706560
70656055504540
01002003004005006007008009001000
INPUT FREQUENCY (MHz)
224012 G11
1V RANGE1V RANGE2V RANGE01002003004005006007008009001000
INPUT FREQUENCY (MHz)
224010 G12
224010fb7
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LTC2240-10TYPICAL PERFORMANCE CHARACTERISTICS
SFDR and SNR vs Sample Rate, 2V Range, fIN = 30MHz, –1dB, LVDS Mode9085SFDR AND SNR (dBFS)80757065
SNR6055
10090
SFDRSFDR (dBc AND dFBS)8070605040302010
0
20406080100120140160180200
SAMPLE RATE (Msps)
224010 G13
(TA = 25°C unless otherwise noted, Note 4)SFDR vs Input Level, fIN = 70MHz, 2V RangedBFS
SNR vs SENSE, fIN = 5MHz, –1dBdBc
0–50
–40
–20–30–10
INPUT LEVEL (dBFS)
0
224212 G14
IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB190180170IVDD (mA)160
1V RANGE150140130220
6050
2V RANGEIOVDD (mA)403020100
IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dBLVDS OUTPUTSOVDD = 2.5VCMOS OUTPUTSOVDD = 1.8V040
160120
SAMPLE RATE (Msps)
80200
224010 G16
040
80120160SAMPLE RATE (Msps)
SNR (dBFS)200
224010 G17
224010fb8
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LTC2240-10PIN FUNCTIONS
(CMOS Mode)AIN+ (Pins 1, 2): Positive Differential Analog Input.AIN– (Pins 3, 4): Negative Differential Analog Input.REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1μF ceramic chip capacitor, to Pins 11, 12 with a 2.2μF ceramic capacitor and to ground with 1μF ceramic capacitor.REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5, 6 with 0.1μF ceramic chip capacitor. Do not connect to Pins 11, 12.REFHB (Pins 9, 10): ADC High Reference. Bypass to Pins 11, 12 with 0.1μF ceramic chip capacitor. Do not connect to Pins 5, 6.REFLA (Pins 11, 12): ADC Low Reference. Bypass to Pins 9, 10 with 0.1μF ceramic chip capacitor, to Pins 5, 6 with a 2.2μF ceramic capacitor and to ground with 1μF ceramic capacitor.VDD (Pins 13, 14, 15, 62, 63): 2.5V Supply. Bypass to GND with 0.1μF ceramic chip capacitors.GND (Pins 16, 61, 64): ADC Power Ground. ENC+ (Pin 17): Encode Input. Conversion starts on the positive edge.ENC– (Pin 18): Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1μF ceramic for single-ended encode signal.SHDN (Pin 19): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance.OE (Pin 20): Output Enable Pin. Refer to SHDN pin func-tion.DNC (Pins 21, 22, 40, 43): Do not connect these pins. DB0-DB9 (Pins 23, 24, 27, 28, 29, 30, 31, 32, 35, 36): Digital Outputs, B Bus. DB9 is the MSB. At high impedance in full rate CMOS mode.OGND (Pins 25, 33, 41, 50): Output Driver Ground.OVDD (Pins 26, 34, 42, 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1μF ceramic chip capacitor.OFB (Pin 37): Over/Under Flow Output for B Bus. High when an over or under fl ow has occurred. At high imped-ance in full rate CMOS mode.CLKOUTB (Pin 38): Data Valid Output for B Bus. In demux mode with interleaved update, latch B bus data on the fall-ing edge of CLKOUTB. In demux mode with simultaneous update, latch B bus data on the rising edge of CLKOUTB. This pin does not become high impedance in full rate CMOS mode.CLKOUTA (Pin 39): Data Valid Output for A Bus. Latch A bus data on the falling edge of CLKOUTA. DA0-DA9 (Pins 44, 45, 46, 47, 48, 51, 52, 53, 54, 55): Digital Outputs, A Bus. DA9 is the MSB.OFA (Pin 56): Over/Under Flow Output for A Bus. High when an over or under fl ow has occurred.LVDS (Pin 57): Output Mode Selection Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demux CMOS mode with simultaneous update. Connecting LVDS to 2/3VDD selects demux CMOS mode with interleaved update. Connecting LVDS to VDD selects LVDS mode.MODE (Pin 58): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and turns the clock duty cycle stabilizer off. Connecting MODE to 1/3VDD selects offset binary output format and turns the clock duty cycle stabilizer on. Connecting MODE to 2/3VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. Connecting MODE to VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off.SENSE (Pin 59): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. Connecting SENSE to VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±VSENSE. ±1V is the largest valid input range.VCM (Pin 60): 1.25V Output and Input Common Mode Bias. Bypass to ground with 2.2μF ceramic chip capacitor.GND (Exposed Pad) (Pin 65): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground.224010fb9
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LTC2240-10PIN FUNCTIONS
(LVDS Mode)AIN+ (Pins 1, 2): Positive Differential Analog Input.AIN– (Pins 3, 4): Negative Differential Analog Input.REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1μF ceramic chip capacitor, to Pins 11, 12 with a 2.2μF ceramic capacitor and to ground with 1μF ceramic capacitor.REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5, 6 with 0.1μF ceramic chip capacitor. Do not connect to Pins 11, 12.REFHB (Pins 9, 10): ADC High Reference. Bypass to Pins 11, 12 with 0.1μF ceramic chip capacitor. Do not connect to Pins 5, 6.REFLA (Pins 11, 12): ADC Low Reference. Bypass to Pins 9, 10 with 0.1μF ceramic chip capacitor, to Pins 5, 6 with a 2.2μF ceramic capacitor and to ground with 1μF ceramic capacitor.VDD (Pins 13, 14, 15, 62, 63): 2.5V Supply. Bypass to GND with 0.1μF ceramic chip capacitors.GND (Pins 16, 61, 64): ADC Power Ground.ENC+ (Pin 17): Encode Input. Conversion starts on the positive edge.ENC– (Pin 18): Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1μF ceramic for single-ended encode signal.SHDN (Pin 19): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance.OE (Pin 20): Output Enable Pin. Refer to SHDN pin func-tion.DNC (Pins 21, 22, 23, 24): Do not connect these pins.D0–/D0+ to D9–/D9+ (Pins 27, 28, 29, 30, 31, 32, 37, 38, 39, 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54): LVDS Digital Outputs. All LVDS outputs require differential 100Ω termination resistors at the LVDS receiver. D9–/D9+ is the MSB.OGND (Pins 25, 33, 41, 50): Output Driver Ground.OVDD (Pins 26, 34, 42, 49): Positive Supply for the Out-put Drivers. Bypass to ground with 0.1μF ceramic chip capacitor.CLKOUT–/CLKOUT+ (Pins 35 to 36): LVDS Data Valid Output. Latch data on rising edge of CLKOUT–, falling edge of CLKOUT+.OF–/OF+ (Pins 55 to 56): LVDS Over/Under Flow Output. High when an over or under fl ow has occurred.LVDS (Pin 57): Output Mode Selection Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demux CMOS mode with simultaneous update. Connecting LVDS to 2/3VDD selects demux CMOS mode with interleaved update. Connecting LVDS to VDD selects LVDS mode.MODE (Pin 58): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and turns the clock duty cycle stabilizer off. Connecting MODE to 1/3VDD selects offset binary output format and turns the clock duty cycle stabilizer on. Connecting MODE to 2/3VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. Connecting MODE to VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off.SENSE (Pin 59): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. Connecting SENSE to VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±VSENSE. ±1V is the largest valid input range.VCM (Pin 60): 1.25V Output and Input Common Mode Bias. Bypass to ground with 2.2μF ceramic chip capacitor.GND (Exposed Pad) (Pin 65): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground.224010fb10
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LTC2240-10FUNCTIONAL BLOCK DIAGRAM
AIN+AIN–INPUTS/HFIRST PIPELINEDADC STAGESECOND PIPELINEDADC STAGETHIRD PIPELINEDADC STAGEFOURTH PIPELINEDADC STAGEFIFTH PIPELINEDADC STAGEGNDVDDVCM2.2μF1.25VREFERENCERANGESELECTSHIFT REGISTERAND CORRECTIONSENSEREFBUFREFHREFLINTERNAL CLOCK SIGNALSOVDD
DIFFREFAMPDIFFERENTIALINPUTLOW JITTERCLOCKDRIVERCONTROLLOGICOUTPUTDRIVERS•••+OF–+D9–+–+–D0CLKOUT
REFLBREFHA2.2μF0.1μF1μFREFLAREFHB0.1μF1μFENC+ENC–M0DELVDSSHDNOEOGND224010 F01Figure 1. Functional Block Diagram224010fb11
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LTC2240-10TIMING DIAGRAMS
LVDS Output Mode Timing All Outputs Are Differential and Have LVDS LevelstAPANALOGINPUT
NtHtLENC–ENC+
tDD0-D9, OF
tCN – 5N – 4N – 3N – 2N – 1N + 1N + 2N + 3N + 4CLKOUT–CLKOUT+
224010 TD01
Full-Rate CMOS Output Mode TimingAll Outputs Are Single-Ended and Have CMOS LevelstAPANALOGINPUT
NtHtLENC–ENC+
tDDA0-DA9, OFA
tCCLKOUTBCLKOUTA
N – 5N – 4N – 3N – 2N – 1N + 1N + 2N + 3N + 4DB0-DB9, OFBHIGH IMPEDANCE
224010 TD02
224010fb12
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LTC2240-10TIMING DIAGRAMS
Demultiplexed CMOS Outputs with Interleaved UpdateAll Outputs Are Single-Ended and Have CMOS LevelstAPANALOGINPUT
NtHENC–ENC+
N + 1N + 2N + 3tLN + 4tDN – 5tDN – 3N – 1DA0-DA9, OFA
DB0-DB9, OFBN – 6tCtCN – 4N – 2CLKOUTBCLKOUTA
224010 TD03Demultiplexed CMOS Outputs with Simultaneous UpdateAll Outputs Are Single-Ended and Have CMOS LevelstAPANALOGINPUT
NtHtLENC–ENC+
tDDA0-DA9, OFA
tDDB0-DB9, OFB
tCCLKOUTBCLKOUTA
224010 TD04
N + 2N + 3N + 1N + 4N – 6N – 4N – 2N – 5N – 3N – 1224010fb13
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LTC2240-10APPLICATIONS INFORMATION
DYNAMIC PERFORMANCESignal-to-Noise Plus Distortion RatioThe signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamen-tal input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency.Signal-to-Noise RatioThe signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the fi rst fi ve harmonics and DC.Total Harmonic DistortionTotal harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as:⎛THD=20Log⎜⎝
2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodula-tion distortion is defi ned as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product.Spurious Free Dynamic Range (SFDR)Spurious free dynamic range is the peak harmonic or spuri-ous noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal.Full Power BandwidthThe full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal.Aperture Delay TimeThe time from when a rising ENC+ equals the ENC– voltage to the instant that the input signal is held by the sample and hold circuit.Aperture Delay JitterThe variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = –20log (2π • fIN • tJITTER)CONVERTER OPERATIONAs shown in Figure 1, the LTC2240-10 is a CMOS pipelined multi-step converter. The converter has fi ve pipelined ADC stages; a sampled analog input will result in a digitized value fi ve cycles later (see the Timing Diagram section). For optimal performance the analog inputs should be driven differentially. The encode input is differential for improved common mode noise immunity. The LTC2240-10 has two phases of operation, determined by the state of the dif-ferential ENC+/ENC– input pins. For brevity, the text will refer to ENC+ greater than ENC– as ENC high and ENC+ less than ENC– as ENC low.(⎞
V2+V3+V4+...Vn/V1⎟⎠
2222)where V1 is the RMS amplitude of the fundamental fre-quency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fi fth.Intermodulation DistortionIf the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency.If two pure sine waves of frequencies fa and fb are ap-plied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 224010fb14
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Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifi er. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplifi ed and output by the residue amplifi er. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa.When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that ENC transitions from low to high, the sampled input is held. While ENC is high, the held input voltage is buffered by the S/H amplifi er which drives the fi rst pipelined ADC stage. The fi rst stage acquires the output of the S/H dur-ing this high phase of ENC. When ENC goes back low, the fi rst stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When ENC goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the fi fth stage ADC for fi nal evaluation.Each ADC stage following the fi rst has additional range to accommodate fl ash and amplifi er offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer.SAMPLE/HOLD OPERATION AND INPUT DRIVESample/Hold OperationFigure 2 shows an equivalent circuit for the LTC2240-10 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input.During the sample phase when ENC is low, the transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. When ENC transitions from low to high, the sampled input LTC2240-10VDD10ΩCPARASITIC1.8pFRON14ΩCPARASITIC1.8pFVDDCSAMPLE2pFRON14ΩCSAMPLE2pFAIN+VDD10ΩAIN–1.5V6kENC+ENC–6k1.5V224010 F02
Figure 2. Equivalent Input Circuitvoltage is held on the sampling capacitors. During the hold phase when ENC is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As ENC transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen.Common Mode BiasFor optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.25V. The VCM output pin (Pin 60) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2μF or greater capacitor.224010fb15
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Input Drive ImpedanceAs with all high performance, high speed ADCs, the dy-namic performance of the LTC2240-10 can be infl uenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can infl uence SFDR. At the falling edge of ENC, the sample-and-hold circuit will connect the 2pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when ENC rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2fS); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling.For the best performance, it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second.Input Drive CircuitsFigure 3 shows the LTC2240-10 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Terminating on the trans-former secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz.Figure 4 demonstrates the use of a differential amplifi er to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies.ANALOGINPUT0.1μFFigure 5 shows a capacitively-coupled input circuit. The im-pedance seen by the analog inputs should be matched. The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from 10ΩVCM2.2μF0.1μF
ANALOGINPUT
T11:125Ω25Ω25Ω0.1μFAIN+AIN+12pF25ΩAIN–AIN–224010 F03
LTC2240-10T1 = MA/COM ETC1-1TRESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 3. Single-Ended to Differential Conversion Using a Transformer50ΩHIGH SPEEDDIFFERENTIALAMPLIFIERVCM2.2μF25Ω3pFAIN+AIN+12pFAIN–3pFAIN–224010 F04+CM+–LTC2240-10–25ΩFigure 4. Differential Drive with an Amplifi erVCM100Ω100Ω25Ω2.2μFAIN+AIN+ANALOGINPUT0.1μF25Ω12pFAIN–AIN–224010 F050.1μFLTC2240-10Figure 5. Capacitively-Coupled Drive224010fb16
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LTC2240-10APPLICATIONS INFORMATION
the sample-and-hold charging glitches and limiting the wideband noise at the converter input. For input frequen-cies higher than 100MHz, the capacitor may need to be decreased to prevent excessive signal loss.The AIN+ and AIN– inputs each have two pins to reduce package inductance. The two AIN+ and the two AIN– pins 10ΩVCM2.2μF0.1μFANALOGINPUTT10.1μF25Ω12Ω25Ω12Ω0.1μFAIN+AIN+8pFAIN–AIN–T1 = MA/COM ETC1-1-13RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
224010 F06LTC2240-10should be shorted together.For input frequencies above 100MHz the input circuits of Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a fl ux coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.25V. In Figure 8 the series inductors are impedance matching elements that maximize the ADC bandwidth.Reference OperationFigure 9 shows the LTC2240-10 reference circuitry consist-ing of a 1.25V bandgap reference, a difference amplifi er and switching and control circuit. The internal voltage reference can be confi gured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range; typing the SENSE pin to VCM selects the 1V range.The 1.25V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifi er to gener-ate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.25V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry.The difference amplifi er generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has four pins: two each of REFHA and REFHB for the high reference and two each of REFLA and REFLB for the low reference. The multiple output pins are needed to reduce package inductance. Bypass capaci-tors must be connected as shown in Figure 9.Figure 6. Recommended Front End Circuit for Input Frequencies Between 100MHz and 250MHz10ΩVCM2.2μF0.1μFANALOGINPUTT10.1μF25Ω25Ω0.1μFAIN+AIN+AIN–AIN–LTC2240-10T1 = MA/COM ETC1-1-13RESISTORS, CAPACITORSARE 0402 PACKAGE SIZE
224010 F07Figure 7. Recommended Front End Circuit for Input Frequencies Between 250MHz and 500MHz10ΩVCM2.2μF0.1μFANALOGINPUTT10.1μF25Ω25Ω2.7nH0.1μFAIN+AIN+AIN–AIN–LTC2240-102.7nHT1 = MA/COM ETC1-1-13RESISTORS, CAPACITORSARE 0402 PACKAGE SIZE
224010 F08Figure 8. Recommended Front End Circuit for Input Frequencies Above 500MHz224010fb17
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LTC2240-101.25VVCM2.2μF2Ω1.25V BANDGAPREFERENCE1VRANGEDETECTANDCONTROLSENSEREFLB0.1μFREFHABUFFERINTERNAL ADCHIGH REFERENCE0.5VInput RangeThe input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 1.7dB. See the Typical Performance Characteristics section.Driving the Encode InputsThe noise performance of the LTC2240-10 can depend on the encode signal quality as much as on the analog input. The ENC+/ENC– inputs are intended to be driven differentially, primarily for noise immunity from com-mon mode noise sources. Each input is biased through a 4.8k resistor to a 1.5V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits.Any noise present on the encode signal will result in ad-ditional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. TIE TO VDD FOR 2V RANGE;TIE TO VCM FOR 1V RANGE;RANGE = 2 • VSENSE FOR0.5V < VSENSE < 1V1μF2.2μFDIFF AMP1μFREFLA0.1μFREFHBINTERNAL ADCLOW REFERENCE224010 F09Figure 9. Equivalent Reference Circuit1.25V8k0.75V12kVCM2.2μFSENSE1μFLTC2240-10In applications where jitter is critical (high input frequen-cies) take the following into consideration:1. Differential drive should be used.2. Use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the ampli-tude.3. If the ADC is clocked with a sinusoidal signal, fi lter the encode signal to reduce wideband noise.4. Balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.2V to 2.0V. Each input may be driven from ground to VDD for single-ended drive.224010 F10Figure 10. 1.5V Range ADCOther voltage ranges in between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by ap-plying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1μF ceramic capacitor.224010fb18
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LTC2240-10VDDTO INTERNALADC CIRCUITSVDDENC50Ω8.2pF0.1μF50ΩENC–0.1μF100ΩVDD1.5V BIAS4.8k+CLOCKINPUTT1MA/COM0.1μFETC1-1-131.5V BIAS4.8k••224010 F11
Figure 11. Transformer Driven ENC+/ENC–VTHRESHOLD = 1.5VENC+1.5VENC–LTC2240-100.1μF224010 F12a
0.1μFLVDSCLOCK
ENC+LTC2240-10100Ω0.1μFENC–224010 F12b
Figure 12a. Single-Ended ENC Drive,Not Recommended for Low JitterFigure 12b. ENC Drive Using LVDSMaximum and Minimum Encode RatesThe maximum encode rate for the LTC2240-10 is 170Msps. For the ADC to operate properly, the encode signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 2.79ns for the ADC internal circuitry to have enough settling time for proper operation. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the ENC+ pin to sample the analog input. The falling edge of ENC+ is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors.The lower limit of the LTC2240-10 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specifi ed minimum operating frequency for the LTC2240-10 is 1Msps.DIGITAL OUTPUTSTable 1 shows the relationship between the analog input voltage, the digital data bits, and the overfl ow bit.224010fb19
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Table 1. Output Codes vs Input VoltageAIN+ – AIN–(2V Range)>+1.000000V+0.998047V+0.996094V+0.001953V0.000000V–0.001953V–0.003906V–0.998047V–1.000000V<–1.000000VOF1000000001D9 – D0(Offset Binary)11 1111 111111 1111 111111 1111 111010 0000 000110 0000 000001 1111 111101 1111 111000 0000 000100 0000 000000 0000 0000D9 – D0(2’s Complement)01 1111 111101 1111 111101 1111 111000 0000 000100 0000 000011 1111 111111 1111 111010 0000 000110 0000 000010 0000 0000Digital Output Buffers (CMOS Modes)Figure 13a shows an equivalent circuit for a single output buffer in the CMOS output mode. Each buffer is powered by OVDD and OGND, which are isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to voltages as low as 0.5V. The internal resistor in series with the output makes the output appear as 50Ω to external circuitry and may eliminate the need for external damping resistors.As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2240-10 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an 74VCX245 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. Lower OVDD voltages will also help reduce interference from the digital outputs.Digital Output Buffers (LVDS Mode)Figure 13b shows an equivalent circuit for a differential output pair in the LVDS output mode. A 3.5mA current is steered from OUT+ to OUT– or vice versa which creates a ±350mV differential voltage across the 100Ω termination resistor at the LVDS receiver. A feedback loop regulates the common mode output voltage to 1.25V. For proper operation each LVDS output pair needs an external 100Ω termination resistor, even if the signal is not used (such as OF+/OF– or CLKOUT+/CLKOUT–). To minimize noise the PC board traces for each LVDS output pair should be routed close together. To minimize clock skew all LVDS PC board traces should have about the same length.Digital Output ModesThe LTC2240-10 can operate in several digital output modes: LVDS, CMOS running at full speed, and CMOS demultiplexed onto two buses, each of which runs at half speed. In the demultiplexed CMOS modes the two buses (referred to as bus A and bus B) can either be updated on alternate clock cycles (interleaved mode) or simultaneously (simultaneous mode). For details on the clock timing, refer to the timing diagrams. The LVDS pin selects which digital output mode the part uses. This pin has a four-level logic input which should be connected to GND, 1/3VDD, 2/3VDD or VDD. An external resistor divider can be used to set the 1/3VDD or 2/3VDD logic values. Table 2 shows the logic states for the LVDS pin.Table 2. LVDS Pin FunctionLVDSGND1/3VDD2/3VDDVDDDIGITAL OUTPUT MODEFull-Rate CMOSDemultiplexed CMOS, Simultaneous UpdateDemultiplexed CMOS, Interleaved UpdateLVDS224010fb20
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LTC2240-10VDDVDDOVDDLTC2240-100.5VTO 2.625V0.1μF
OVDDDATAFROMLATCHOEPREDRIVERLOGIC43ΩTYPICALDATAOUTPUTOGND3.5mAD10k1.25VDD10kDOUT+100ΩOUT–LVDSRECEIVEROVDD0.1μF2.5V224010 F13a
OGND224010 F13bFigure 13a. Digital Output Buffer in CMOS ModeFigure 13b. Digital Output in LVDS ModeData FormatThe LTC2240-10 parallel digital output can be selected for offset binary or 2’s complement format. The format is selected with the MODE pin. Connecting MODE to GND or 1/3VDD selects offset binary output format. Connecting MODE to 2/3VDD or VDD selects 2’s complement output format. An external resistor divider can be used to set the 1/3VDD or 2/3VDD logic values. Table 3 shows the logic states for the MODE pin.Table 3. MODE Pin FunctionMODE PINGND1/3VDD2/3VDDVDDOUTPUT FORMATOffset BinaryOffset Binary2’s Complement2’s ComplementCLOCK DUTYCYCLE STABILIZEROffOnOnOffOutput ClockThe ADC has a delayed version of the ENC+ input available as a digital output, CLKOUT. The CLKOUT pin can be used to synchronize the converter data to the digital system. +
This is necessary when using a sinusoidal encode. In –
all CMOS modes, A bus data will be updated just after CLKOUTA rises and can be latched on the falling edge of CLKOUTA. In demux CMOS mode with interleaved update, B bus data will be updated just after CLKOUTB rises and can be latched on the falling edge of CLKOUTB. In demux CMOS mode with simultaneous update, B bus data will be updated just after CLKOUTB falls and can be latched on the rising edge of CLKOUTB. In LVDS mode, data will be updated just after CLKOUT+/CLKOUT– rises and can be latched on the falling edge of CLKOUT+/CLKOUT–.Output Driver PowerSeparate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example if the converter is driving a DSP powered by a 1.8V supply then OVDD should be tied to that same 1.8V supply.Overfl ow BitAn overfl ow output bit indicates when the converter is overranged or underranged. In CMOS mode, a logic high on the OFA pin indicates an overfl ow or underfl ow on the A data bus, while a logic high on the OFB pin indicates an overfl ow or underfl ow on the B data bus. In LVDS mode, a differential logic high on the OF+/OF– pins indicates an overfl ow or underfl ow.224010fb21
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In the CMOS output mode, OVDD can be powered with any voltage up to 2.625V. OGND can be powered with any voltage from GND up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD.In the LVDS output mode, OVDD should be connected to a 2.5V supply and OGND should be connected to GND.Output EnableThe outputs may be disabled with the output enable pin, OE. In CMOS or LVDS output modes OE high disables all data outputs including OF and CLKOUT. The data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. The output Hi-Z state is intended for use during long periods of inactivity. The Hi-Z state is not a truly open circuit; the output pins that make an LVDS output pair have a 20k resistance be-tween them. Therefore in the CMOS output mode, adjacent data bits will have 20k resistance in between them, even in the Hi-Z state.Sleep and Nap ModesThe converter may be placed in shutdown or nap modes to conserve power. Connecting SHDN to GND results in normal operation. Connecting SHDN to VDD and OE to VDD results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mW. When exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. Connecting SHDN to VDD and OE to GND results in nap mode, which typically dis-sipates 28mW. In nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. In both sleep and nap mode all digital outputs are disabled and enter the Hi-Z state.GROUNDING AND BYPASSINGThe LTC2240-10 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital signal alongside an analog signal or underneath the ADC.High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM, REFHA, REFHB, REFLA and REFLB pins. Bypass capacitors must be located as close to the pins as possible. Of particular importance are the capaci-tors between REFHA and REFLB and between REFHB and REFLA. These capacitors should be as close to the device as possible (1.5mm or less). Size 0402 ceramic capacitors are recommended. The 2.2μF capacitor between REFHA and REFLA can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible.The LTC2240-10 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup.HEAT TRANSFERMost of the heat generated by the LTC2240-10 is trans-ferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the PC board. It is critical that all ground pins are connected to a ground plane of suffi cient area.Clock Sources for UndersamplingUndersampling is especially demanding on the clock source and the higher the input frequency, the greater the sensitivity to clock jitter or phase noise. A clock source that degrades SNR of a full-scale signal by 1dB at 70MHz will degrade SNR by 3dB at 140MHz, and 4.5dB at 190MHz.In cases where absolute clock frequency accuracy is relatively unimportant and only a single ADC is required, a canned oscillator from vendors such as Saronix or Vectron can be placed close to the ADC and simply connected directly to the ADC. If there is any distance to the ADC, 224010fb22
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some source termination to reduce ringing that may occur even over a fraction of an inch is advisable. You must not allow the clock to overshoot the supplies or performance will suffer. Do not fi lter the clock signal with a narrow band fi lter unless you have a sinusoidal clock source, as the rise and fall time artifacts present in typical digital clock signals will be translated into phase noise. The lowest phase noise oscillators have single-ended sinusoidal outputs, and for these devices the use of a fi lter close to the ADC may be benefi cial. This fi lter should be close to the ADC to both reduce roundtrip refl ection times, as well as reduce the susceptibility of the traces between the fi lter and the ADC. If the circuit is sensitive to close-in phase noise, the power supply for oscillators and any buffers must be very stable, or propagation de-lay variation with supply will translate into phase noise. Even though these clock sources may be regarded as digital devices, do not operate them on a digital supply. If your clock is also used to drive digital devices such as an FPGA, you should locate the oscillator, and any clock fan-out devices close to the ADC, and give the routing to the ADC precedence. The clock signals to the FPGA should have series termination at the driver to prevent high frequency noise from the FPGA disturbing the sub-strate of the clock fan-out device. If you use an FPGA as a programmable divider, you must re-time the signal using the original oscillator, and the re-timing fl ip-fl op as well as the oscillator should be close to the ADC, and powered with a very quiet supply.For cases where there are multiple ADCs, or where the clock source originates some distance away, differential clock distribution is advisable. This is advisable both from the perspective of EMI, but also to avoid receiving noise from digital sources both radiated, as well as propagated in the waveguides that exist between the layers of multilayer PCBs. The differential pairs must be close together and distanced from other signals. The differential pair should be guarded on both sides with copper distanced at least 3x the distance between the traces, and grounded with vias no more than 1/4 inch apart. 224010fb23
C25 0.1μFC26 0.1μF2.5VR912.4ΩR134.99Ω656461166362151413GNDGNDGNDGNDVDDVDDVDDVDDVDDR3100Ω45I1NI1PO1NO1PO2NO2PO3NO3PO4NO4PO5NO5P33323534393841404342I2NI2PI3NI3PI4NI4PI5NI5P67R18100ΩR19100ΩR20100ΩR21100ΩR22100Ω1617I6NI6PO6NO6PR28 100Ω1819I7NI7PI8NI8PVBBVE1VE2VE3VE4VE5202124R30 100Ω14151011894544J5SMAC60.1μFT1MABA-007159-000000LTC2240-10AIN322274613R1149.9ΩR1012.4ΩR144.99ΩR17100ΩR23100ΩC91.8pFLTC2240-10U3 FINII08EN12EN34EN56EN78ENC70.1μFR1249.9ΩR2749.9ΩC151μFR1549.9ΩC172.2μFC161μF1718ENC+ENC–VCMO7NO7PO8NO8P60C140.1μF10REFHB9REFHB12REFLA11REFLAC130.1μFVC1VC2VC3VC4VC51225264748元器件交易网www.cecb2b.com
APPLICATIONS INFORMATIONTP6VCM24625OGND33OGND41OGND50OGND26OVDD34OVDD42OVDD49OVDDSHDN 3VDD 1GND 54OE2 VDD6 GNDJ4SENSE2.5VTP1EXT REFTP2GNDR6 1kC20 0.1μFJ2MODE 1VDD 3GND 524 2/36 1/3R71kC22 0.1μFC23 0.1μFR40100ΩR37BLM18BB470SN1DR43100Ω+3.3VR42100ΩR8 1kC21 0.1μFR38100ΩR39100ΩC190.1μF2.5VVC1VC2VC3VC4VC52.5V 1VCM 3EXT REF 51225264748OF+/OFAOF–/DA9D9+/DA8D9–/DA7D8+/DA6D8–/DA5D7+/DA4D7–/DA3D6+/DA2D6–/DA1D5+/DA0D5–/DNCD4+/DNCD4–/CLKOUTAD3+/CLKOUTBD3–/OFBCLKOUT+/DB9CLKOUT–/DB8D2+/DB7D2–/DB6D1+/DB5D1–/DB4D0+/DB3D0–/DB2DNC/DB1DNC/DB0DNCDNC313029283.3V12233637C340.1μFINU5SENBYP56VOSJ2SHDNGNDGP7GPR251k8113ARRAYEEPROMVERSION DEVICE BITS SAMPLERATEDC997B-A LTC2242-12 12 250MspsDC997B-B LTC2241-12 12 210MspsDC997B-C LTC2240-12 12 170MspsDC997B-D LTC2242-10 10 250MspsDC997B- LTC2241-10 10 210MspsDC997B-F LTC2240-10 10 170Msps1C280.1μFC290.1μFC300.1μFC310.1μFC320.1μFC330.1μFLVDS BUFFER BYPASSC50.1μFC80.1μF12233637VE1VE2VE3VE4VE524
Evaluation Circuit Schematic of the LTC2240-103.3V21436587AIN+AIN+AIN–AIN–REFHAREFHAREFLBREFLB2.5VR241k1920595857SHDNOESENSEMODELVDS56555453525148474645444340393837363532313029282724232221246810121416182022242628303234363840424446485052541357911131517192123252729313335373941434547495153322274613456789101114151617+2.5V2C2410μFC380.01μF3.3V1819202124U3 FINII08EN12EN34EN56EN78ENI1NI1PI2NI2PI3NI3PI4NI4PI5NI5PI6NI6PI7NI7PO1NO1PO2NO2PO3NO3PO4NO4PO5NO5PO6NO6PO7NO7P45444342414039383534333231302928I8NI8PVBBO8NO8PR16100k8VCC2.5VR294990Ω565860626466687072747678808284868890929496981005557596163656769717375777981838587899193959799R464990ΩR264990ΩC270.1μF24LC02ST10INVOLT1763CDE-2.5GND4224010AI01C120.1μFC100.1μFC182.2μFJ7ENCODEC2CLK0.1μFT2MABA-007159-000000SMAR44.99ΩR149.9ΩC10.1μFR249.9ΩC41.8pFR41100ΩC110.1μFC30.1μFR54.99ΩE3.3V TP5GND TP42.5V TP3(NO TURRET)J6AUX PWRCONNECTOR123C364.7μFSCLSDAWPA2A1A0657321224010fbLTC2240-10APPLICATIONS INFORMATION
Silkscreen TopLayer 2 GND PlaneLayer 1 Component SideLayer 3 Power/Ground Plane224010fb25
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LTC2240-10APPLICATIONS INFORMATION
Layer 4 Power/Ground PlanesLayer Back Solder SideLayer 5 Power/Ground PlanesSilk Screen Back, Solder Side224010fb26
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LTC2240-10PACKAGE DESCRIPTION
UP Package64-Lead Plastic QFN (9mm × 9mm)(Reference LTC DWG # 05-08-1705)RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS0.70 ±0.057.15 ±0.058.10 ±0.059.50 ±0.05(4 SIDES)NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-52. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT,
SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE
PACKAGE OUTLINE0.25 ±0.050.50 BSC9 .00 ± 0.10(4 SIDES)0.75 ± 0.05BOTTOM VIEW—EXPOSED PADR = 0.115TYP63640.40 ± 0.1012PIN 1 TOP MARK(SEE NOTE 5)PIN 1CHAMFER7.15 ± 0.10(4-SIDES)0.200 REF0.00 – 0.050.25 ± 0.050.50 BSC(UP64) QFN 1003224010fbInformation furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.27
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LTC2240-10RELATED PARTS
PART NUMBERLTC1748LTC1750LT®1993-2LT1994LTC2202LTC2208LTC2220LTC2220-1LTC2221LTC2224LTC2230LTC2231LTC2240-12LTC2241-10LTC2241-12LTC2242-10LTC2242-12LTC2255LTC2284LT5512LT5514LT5515LT5516LT5517LT5522DESCRIPTION14-Bit, 80Msps, 5V ADC14-Bit, 80Msps, 5V Wideband ADCHigh Speed Differential Op AmpLow Noise, Low Distortion Fully Differential Input/Output Amplifi er/Driver16-Bit, 10Msps, 3.3V ADC, Lowest Noise16-Bit, 130Msps, 3.3V ADC, LVDS Outputs12-Bit, 170Msps, 3.3V ADC, LVDS Outputs12-Bit, 185Msps, 3.3V ADC, LVDS Outputs12-Bit, 135Msps, 3.3V ADC, LVDS Outputs12-Bit, 135Msps, 3.3V ADC, High IF Sampling10-Bit, 170Msps, 3.3V ADC, LVDS Outputs10-Bit, 135Msps, 3.3V ADC, LVDS Outputs12-Bit, 170Msps, 2.5V ADC, LVDS Outputs10-Bit, 210Msps, 2.5V ADC, LVDS Outputs12-Bit, 210Msps, 2.5V ADC, LVDS Outputs10-Bit, 250Msps, 2.5V ADC, LVDS Outputs12-Bit, 250Msps, 2.5V ADC, LVDS Outputs14-Bit, 125Msps, 3V ADC, Lowest Power14-Bit, Dual, 105Msps, 3V ADC, Low CrosstalkDC to 3GHz High Signal Level Downconverting MixerUltralow Distortion IF Amplifi er/ADC Driver with Digitally Controlled Gain1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator800MHz to 1.5GHz Direct Conversion Quadrature Demodulator40MHz to 900MHz Direct Conversion Quadrature Demodulator600MHz to 2.7GHz High Linearity Downconverting MixerCOMMENTS76.3dB SNR, 90dB SFDR, 48-Pin TSSOPUp to 500MHz IF Undersampling, 90dB SFDR800MHz BW, 70dBc Distortion at 70MHz, 6dB GainLow Distortion: –94dBc at 1MHz150mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN1250mW, 78dB SNR, 100dB SFDR, 48-Pin QFN890mW, 67.7dB SNR, 84dB SFDR, 64-Pin QFN910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN660mW, 67.8dB SNR, 84dB SFDR, 64-Pin QFN630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN890mW, 61.2dB SNR, 78dB SFDR, 64-Pin QFN660mW, 61.2dB SNR, 78dB SFDR, 64-Pin QFN445mW, 65.6dB SNR, 80dB SFDR, 64-Pin QFN585mW, 60.6dB SNR, 78dB SFDR, 64-Pin QFN585mW, 65.6dB SNR, 80dB SFDR, 64-Pin QFN740mW, 60.5dB SNR, 78dB SFDR, 64-Pin QFN745mW, 65.6dB SNR, 80dB SFDR, 64-Pin QFN395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFNDC to 3GHz, 21dBm IIP3, Integrated LO Buffer450MHz to 1dB BW, 47dB OIP3, Digital Gain Control10.5dB to 33dB in 1.5dB/StepHigh IIP3: 20dBm at 1.9GHz, Integrated LOQuadrature GeneratorHigh IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature GeneratorHigh IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB,50Ω Single-Ended RF and LO Ports224010fb28
Linear Technology CorporationLT 1107 REV B • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com© LINEAR TECHNOLOGY CORPORATION 2006
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