METHOD OF MAKING INTEGRATED CIRCUITS

专利名称：METHOD OF MAKING INTEGRATED

CIRCUITS

发明人：CHARLES R. COOK JR.申请号：US3484932D申请日：19681009公开号：US3484932A公开日：19691223

摘要：1,001,908. Semi-conductor devices. TEXAS INSTRUMENTS Inc. Dec. 31, 1962[Aug. 31, 1962], No. 49041/62. Heading H1K. [Also in Division H3] Interconnectionsbetween the various parts of a solid circuit formed in a semi-conductor wafer are madeby depositing conductive material over the entire insulation coated face of the wafer tomake contacts through opertures in the coating and then selectively removing it to leaveonly the required interconnections. A wafer containing a plurality of groups oftransistors, capacitors, diode rectifiers and resistors, each capable of providing severaldifferent circuits with suitable interconnections is fabricated as follows: A 10- 15 ohm. cm.doped P-type silicon wafer, after polishing, etching and cleaning is coated with oxide byheating in steam. A repeating pattern of the group of apertures shown in Fig. 6 is formedin the oxide by photo-resist masking and etching techniques. Phosphorus is depositedand diffused into the wafer through the apertures to form N regions constituting thespiral and linear, resistor tracks, collector zones of the transistors, cathode zones of thediodes and zones of the NPN capacitors. During the process the oxide reforms in theapertures. A different pattern of apertures is then formed in register with the first by thesame method and boron diffused through the apertures to form P zones constituting

the transistor base zones, diode anode zones and the P zones of the capacitors. Thetransistor emitter zones and the outer N zones of the capacitors are next formed bydiffusion from a mixture of oxygen and phosphorus pertoxide vapour through a thirdmask. Finally, apertures are formed in the oxide layer by a photo-resist masking andetching process to expose a portion of each zone of each circuit element. Each group ofelements then appears as shown in Fig. 1, and consists of transistors 28-34, PN diodes 35-41, linear tapped resistors 25-27, spiral resistors 19-24 attached to an N zone of the NPNcapacitors 13-18 respectively and large NPN capacitors 11 and 12. The logic circuits ofFigs. 22 and 25 (not shown), and the flipflop circuit of Fig. 27 (not shown), can be formedfrom each group of elements in the resulting wafer by deposition of appropriatealuminium interconnections as in Figs. 21, 24 and 26 respectively (also not shown). Thisprocess is effected by vacuum evaporation of aluminium while the wafer is heated toslightly below the temperature of the aluminium-silicon eutectic. The energy of thebombarding aluminium atoms raises the temperature locally to the eutectic to formgood atomic contact with the silicon in the apertures. A further photo-resist masking andetching step is used to remove the unwanted aluminium between the desiredinterconnections. After etching the back surface to reduce the wafer to the desiredthickness it is scribed and broken up into single circuits. Each of these is mounted bysolder glass on a ceramic wafer and connected by gold wires to metal tabs extendingthrough the solder glass sealing a ceramic ring about the circuit. After applying varnishover the circuit and wires a lid is placed on the ceramic ring to form a hermetic enclosure.Use of germanium and A m B v compounds in place of silicon is also suggested.Specification 958,241 is referred to.

申请人：TEXAS INSTRUMENTS INC.

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