EDA十进制计数设计

一、实验要求：

设计一个带有计数允许输入端、复位输入端和进位输入端的十进制计数器。（备注：基于EP2C8Q208C8芯片开发板） 二、实验设计：

1.分频器模块： 源程序：singal LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY singal IS

GENERIC(N:INTEGER:=25); PORT(

CLKIN:IN STD_LOGIC; CLKOUT:OUT STD_LOGIC );

END singal;

ARCHITECTURE A OF singal IS

SIGNAL CNT:STD_LOGIC_VECTOR(N-1 DOWNTO 0); BEGIN

PROCESS(CLKIN) BEGIN

IF(CLKIN'EVENT AND CLKIN='1')THEN CNT<=CNT+1; END IF;

END PROCESS;

CLKOUT<=CNT(N-1); END A;

仿真图

2．计数模块 源程序：Cnt10 library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity cnt10 is port(res:in std_logic; clkin:in std_logic; ep:in std_logic; cout: out std_logic ; sout:out std_logic_vector(3 downto 0)); end cnt10;

architecture behave of cnt10 is signal count :std_logic_vector(3 downto 0); begin process(res,clkin,ep) begin if(res='1') then count<=\"0000\";cout<='0'; elsif(ep='0' and rising_edge(clkin)) then if(count=\"1001\") then cout<='1';count<=\"0000\"; else count<=count+1;cout<='0'; end if; end if; end process; sout<=count; end;

仿真图

3.数码管模块

源程序：yimaguan library ieee;

use ieee.std_logic_1164.all; entity yimaguan is port (data_in :in std_logic_vector(3 downto 0); data_out : out std_logic_vector(6 downto 0)); end yimaguan;

architecture behave of yimaguan is begin

process(data_in) begin

case data_in is

when \"0000\"=>data_out<=\"1000000\";

when \"0001\"=>data_out<=\"1111001\"; when \"0010\"=>data_out<=\"0100100\"; when \"0011\"=>data_out<=\"0110000\"; when \"0100\"=>data_out<=\"0011001\"; when \"0101\"=>data_out<=\"0010010\"; when \"0110\"=>data_out<=\"0000010\"; when \"0111\"=>data_out<=\"1111000\"; when \"1000\"=>data_out<=\"0000000\"; when \"1001\"=>data_out<=\"0010000\"; when \"1010\"=>data_out<=\"0001000\"; when \"1011\"=>data_out<=\"0000011\"; when \"1100\"=>data_out<=\"1000110\"; when \"1101\"=>data_out<=\"0100001\"; when \"1110\"=>data_out<=\"0000110\"; when \"1111\"=>data_out<=\"0001110\"; end case; end process; end behave;

仿真图

顶层文件设计：

原理图设计

波形图

仿真图

放大仿真图

仿真图分析：

当出入信号clk为1，ep、res为0时，输出reg波形正常，则此仿真验证设计正确。