元器件交易网www.cecb2b.com SCLS119B – DECEMBER 1982 – REVISED MAY 1997SN54HC174, SN74HC174HEX D-TYPE FLIP-FLOPSWITH CLEARDContain Six Flip-Flops With Single-RailDDOutputsApplications Include:– Buffer/Storage Registers– Shift Registers– Pattern GeneratorsPackage Options Include PlasticSmall-Outline (D) and Ceramic Flat (W)Packages, Ceramic Chip Carriers (FK), andStandard Plastic (N) and Ceramic (J)300-mil DIPsSN54HC174...J OR W PACKAGESN74HC174...D OR N PACKAGE(TOP VIEW)CLR1Q1D2D2Q3D3QGND12345678161514131211109VCC6Q6D5D5Q4D4QCLKdescriptionThese monolithic positive-edge-triggered D-typeflip-flops have a direct clear (CLR) input.Information at the data (D) inputs meeting thesetup time requirements is transferred to theoutputs on the positive-going edge of the clock(CLK) pulse. Clock triggering occurs at aparticular voltage level and is not directly relatedto the transition time of the positive-going edge ofCLK. When CLK is at either the high or low level,the D input has no effect at the output.The SN54HC174 is characterized for operationover the full military temperature range of –55°Cto 125°C. The SN74HC174 is characterized foroperation from –40°C to 85°C.FUNCTION TABLE(each flip-flop)INPUTSCLRLHHHCLKX↑↑LDXHLXOUTPUTQLHLQ0 SN54HC174...FK PACKAGE(TOP VIEW)1D2DNC2Q3D1QCLRNCVCC6Q45678321201918171615149101112136D5DNC5Q4DNC – No internal connectionPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Copyright © 1997, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•3QGNDNCCLK4Q1元器件交易网www.cecb2b.comSCLS119B – DECEMBER 1982 – REVISED MAY 1997SN54HC174, SN74HC174HEX D-TYPE FLIP-FLOPSWITH CLEARlogic symbol† CLRCLK1D2D3D4D5D6D19346111314RC11D2571012151Q2Q3Q4Q5Q6Q†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.Pin numbers shown are for the D, J, N, and W packages.logic diagram (positive logic)CLR1CLK1D931DC1R21QTo Five Other ChannelsPin numbers shown are for the D, J, N, and W packages.absolute maximum ratings over operating free-air temperature range‡Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 VInput clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mAOutput clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mAContinuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mAContinuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mAPackage thermal impedance, θJA (see Note 2):D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/WN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/WStorage temperature range, Tstg –65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°C‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTES:1.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.2.The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a tracelength of zero.2POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com SCLS119B – DECEMBER 1982 – REVISED MAY 1997SN54HC174, SN74HC174HEX D-TYPE FLIP-FLOPSWITH CLEARrecommended operating conditionsSN54HC174MINVCCVIHSupply voltageHigh-level input voltageVCC = 2 VVCC = 4.5 VVCC = 6 VVCC = 2 VVILVIVOttTALow-level input voltageInput voltageOutput voltageInput transition (rise and fall) timeOperating free-air temperatureVCC = 2 VVCC = 4.5 VVCC = 6 VVCC = 4.5 VVCC = 6 V21.53.154.200000000–550.51.351.8VCCVCC1000500400125NOM5MAX6SN74HC174MIN21.53.154.200000000–400.51.351.8VCCVCC100050040085°CnsVVVVNOM5MAX6UNITVelectrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)PARAMETERTESTCONDITIONSTEST CONDITIONSVCC2 VIOH = –20 µAVOHVI = VIH or VILIOH = –4 mAIOH = –5.2 mAIOL = 20 µAVOLVI = VIH or VILIOL = 4 mAIOL = 5.2 mAIIICCCiVI = VCC or 0VI = VCC or 0,IO = 04.5 V6 V4.5 V6 V2 V4.5 V6 V4.5 V6 V6 V6 V2 V to 6 V3TA = 25°CMINTYPMAX1.94.45.93.985.481.9984.4995.9994.35.80.0020.0010.0010.170.15±0.10.10.10.10.260.26±100810SN54HC174MIN1.94.45.93.75.20.10.10.10.40.4±100016010MAXSN74HC174MIN1.94.45.93.845.340.10.10.10.330.33±10008010nAµApFVVMAXUNITPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•3元器件交易网www.cecb2b.comSCLS119B – DECEMBER 1982 – REVISED MAY 1997SN54HC174, SN74HC174HEX D-TYPE FLIP-FLOPSWITH CLEAR timing requirements over recommended operating free-air temperature range (unless otherwisenoted)VCC2 VfclockClock frequency4.5 V6 V2 VCLR lowtwPulsedurationPulse durationCLK high or low4.5 V6 V2 V4.5 V6 V2 VDatatsuSetuptimebeforeCLK↑Setup time before CLKCLR inactive4.5 V6 V2 V4.5 V6 V2 VthHold time, data after CLK↑4.5 V6 VTA = 25°CMINMAX0008016148016141002017100201700063136SN54HC174MIN0001202420120242015030251503025000MAX4.22125SN74HC174MIN0001002017100201712525211252521000nsnsnsMAX52529MHzUNITswitching characteristics over recommended operating free-air temperature range, CL = 50 pF(unless otherwise noted) (see Figure 1)PARAMETERFROM(INPUT)TO(OUTPUT)VCC2 Vfmax4.5 V6 V2 VCLRtpddCLKAnyAny4.5 V6 V2 V4.5 V6 V2 VttAny4.5 V6 VTA = 25°CMINTYPMAX6313694450581714581714388616032271603227751513SN54HC174MIN4.22125240484124048411102219MAXSN74HC174MIN5252920040342004034901916nsnsMHzMAXUNIToperating characteristics, TA = 25°CPARAMETERCpdPower dissipation capacitance per flip-flopTEST CONDITIONSNo loadTYP27UNITpF4POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com SCLS119B – DECEMBER 1982 – REVISED MAY 1997SN54HC174, SN74HC174HEX D-TYPE FLIP-FLOPSWITH CLEARPARAMETER MEASUREMENT INFORMATIONHigh-LevelPulse50%twLow-LevelPulseVCC50%50%0 VVOLTAGE WAVEFORMSPULSE DURATIONSVCC50%tPLHReferenceInputtsuDataInput50%10%90%tr50%th90%VCC50%10%0 VtfOut-of-PhaseOutputVCC0 VIn-PhaseOutput50%10%tPHL90%50%10%tf90%trtPLH50%10%90%tr50%0 VtPHL90%50%10%VOLtfVOHVCC50%0 VFrom OutputUnder TestTestPointCL = 50 pF(see Note A)LOAD CIRCUITInputVOHVOLVOLTAGE WAVEFORMSSETUP AND HOLD AND INPUT RISE AND FALL TIMESVOLTAGE WAVEFORMSPROPAGATION DELAY AND OUTPUT TRANSITION TIMESNOTES:A.CL includes probe and test-fixture capacitance.B.Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the followingcharacteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.C.For clock inputs, fmax is measured when the input duty cycle is 50%.D.The outputs are measured one at a time with one input transition per measurement.E.tPLH and tPHL are the same as tpd.Figure 1. Load Circuit and Voltage WaveformsPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•5元器件交易网www.cecb2b.com
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