FIR滤波器

USElpm.lpm_components.ALL;LIBRARYieee;

USEieee.std_logic_1164.ALL;USEieee.std_logic_arith.ALL;USEieee.std_logic_unsigned.ALL;

--Usingpredefinedpackages

ENTITYfir_genIS------>InterfaceGENERIC(W1:INTEGER:=9;--Inputbitwidth

W2:INTEGER:=18;--Multiplierbitwidth2*W1W3:INTEGER:=19;--Adderwidth=W2+log2(L)-1W4:INTEGER:=11;--OutputbitwidthL:INTEGER:=4;--Filterlength

Mpipe:INTEGER:=3--Pipelinestepsofmultiplier

);

PORT(clk:INSTD_LOGIC;

Load_x:INSTD_LOGIC;x_in:INSTD_LOGIC_VECTOR(W1-1DOWNTO0);c_in:INSTD_LOGIC_VECTOR(W1-1DOWNTO0);y_out:OUTSTD_LOGIC_VECTOR(W4-1DOWNTO0));

ENDfir_gen;

ARCHITECTUREfpgaOFfir_genIS

SUBTYPEN1BITISSTD_LOGIC_VECTOR(W1-1DOWNTO0);SUBTYPEN2BITISSTD_LOGIC_VECTOR(W2-1DOWNTO0);SUBTYPEN3BITISSTD_LOGIC_VECTOR(W3-1DOWNTO0);TYPEARRAY_N1BITISARRAY(0TOL-1)OFN1BIT;TYPEARRAY_N2BITISARRAY(0TOL-1)OFN2BIT;TYPEARRAY_N3BITISARRAY(0TOL-1)OFN3BIT;SIGNALSIGNALSIGNALSIGNALSIGNALBEGIN

Load:PROCESSBEGIN

------>Loaddataorcoefficient

x:N1BIT;y:N3BIT;

c:ARRAY_N1BIT;--Coefficientarrayp:ARRAY_N2BIT;--Productarraya:ARRAY_N3BIT;--Adderarray

WAITUNTILclk='1';IF(Load_x='0')THENc(L-1)<=c_in;--Storecoefficientinregister

FORIINL-2DOWNTO0LOOP--Coefficientsshiftonec(I)<=c(I+1);ENDLOOP;ELSE

x<=x_in;--GetonedatasampleatatimeENDIF;

ENDPROCESSLoad;

SOP:PROCESS(clk)------>Computesum-of-productsBEGIN

IFclk'eventand(clk='1')THENFORIIN0TOL-2LOOP--Computethetransposeda(I)<=(p(I)(W2-1)&p(I))+a(I+1);--filteraddsENDLOOP;

a(L-1)<=p(L-1)(W2-1)&p(L-1);--FirstTAPhasENDIF;--onlyaregistery<=a(0);

ENDPROCESSSOP;

--InstantiateLpipelinedmultiplier

MulGen:FORIIN0TOL-1GENERATEMuls:lpm_mult--Multiplyp(i)=c(i)*x;

GENERICMAP(LPM_WIDTHA=>W1,LPM_WIDTHB=>W1,

LPM_PIPELINE=>Mpipe,

LPM_REPRESENTATION=>\"SIGNED\LPM_WIDTHP=>W2,LPM_WIDTHS=>W2)

PORTMAP(clock=>clk,dataa=>x,

datab=>c(I),result=>p(I));

ENDGENERATE;y_out<=y(W3-1DOWNTOW3-W4);ENDfpga;